1fe8b45aaSThierry Reding# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2fe8b45aaSThierry Reding%YAML 1.2 3fe8b45aaSThierry Reding--- 4fe8b45aaSThierry Reding$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-epp.yaml# 5fe8b45aaSThierry Reding$schema: http://devicetree.org/meta-schemas/core.yaml# 6fe8b45aaSThierry Reding 7fe8b45aaSThierry Redingtitle: NVIDIA Tegra Encoder Pre-Processor 8fe8b45aaSThierry Reding 9fe8b45aaSThierry Redingmaintainers: 10fe8b45aaSThierry Reding - Thierry Reding <thierry.reding@gmail.com> 11fe8b45aaSThierry Reding - Jon Hunter <jonathanh@nvidia.com> 12fe8b45aaSThierry Reding 13fe8b45aaSThierry Redingproperties: 14fe8b45aaSThierry Reding $nodename: 15fe8b45aaSThierry Reding pattern: "^epp@[0-9a-f]+$" 16fe8b45aaSThierry Reding 17fe8b45aaSThierry Reding compatible: 18fe8b45aaSThierry Reding enum: 19fe8b45aaSThierry Reding - nvidia,tegra20-epp 20fe8b45aaSThierry Reding - nvidia,tegra30-epp 21fe8b45aaSThierry Reding - nvidia,tegra114-epp 22fe8b45aaSThierry Reding 23fe8b45aaSThierry Reding reg: 24fe8b45aaSThierry Reding maxItems: 1 25fe8b45aaSThierry Reding 26fe8b45aaSThierry Reding interrupts: 27fe8b45aaSThierry Reding maxItems: 1 28fe8b45aaSThierry Reding 29fe8b45aaSThierry Reding clocks: 30fe8b45aaSThierry Reding maxItems: 1 31fe8b45aaSThierry Reding 32fe8b45aaSThierry Reding resets: 33fe8b45aaSThierry Reding items: 34fe8b45aaSThierry Reding - description: module reset 35fe8b45aaSThierry Reding 36fe8b45aaSThierry Reding reset-names: 37fe8b45aaSThierry Reding items: 38fe8b45aaSThierry Reding - const: epp 39fe8b45aaSThierry Reding 40fe8b45aaSThierry Reding iommus: 41fe8b45aaSThierry Reding maxItems: 1 42fe8b45aaSThierry Reding 43fe8b45aaSThierry Reding interconnects: 44fe8b45aaSThierry Reding maxItems: 4 45fe8b45aaSThierry Reding 46fe8b45aaSThierry Reding interconnect-names: 47fe8b45aaSThierry Reding maxItems: 4 48fe8b45aaSThierry Reding 49*21fd06dcSKrzysztof Kozlowski operating-points-v2: true 50fe8b45aaSThierry Reding 51fe8b45aaSThierry Reding power-domains: 52fe8b45aaSThierry Reding items: 53fe8b45aaSThierry Reding - description: phandle to the core power domain 54fe8b45aaSThierry Reding 55fe8b45aaSThierry RedingadditionalProperties: false 56fe8b45aaSThierry Reding 57fe8b45aaSThierry Redingexamples: 58fe8b45aaSThierry Reding - | 59fe8b45aaSThierry Reding #include <dt-bindings/clock/tegra20-car.h> 60fe8b45aaSThierry Reding #include <dt-bindings/interrupt-controller/arm-gic.h> 61fe8b45aaSThierry Reding 62fe8b45aaSThierry Reding epp@540c0000 { 63fe8b45aaSThierry Reding compatible = "nvidia,tegra20-epp"; 64fe8b45aaSThierry Reding reg = <0x540c0000 0x00040000>; 65fe8b45aaSThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 66fe8b45aaSThierry Reding clocks = <&tegra_car TEGRA20_CLK_EPP>; 67fe8b45aaSThierry Reding resets = <&tegra_car 19>; 68fe8b45aaSThierry Reding reset-names = "epp"; 69fe8b45aaSThierry Reding }; 70