1*a0c70244SSvyatoslav Ryhel# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*a0c70244SSvyatoslav Ryhel%YAML 1.2 3*a0c70244SSvyatoslav Ryhel--- 4*a0c70244SSvyatoslav Ryhel$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra114-tsec.yaml# 5*a0c70244SSvyatoslav Ryhel$schema: http://devicetree.org/meta-schemas/core.yaml# 6*a0c70244SSvyatoslav Ryhel 7*a0c70244SSvyatoslav Ryheltitle: NVIDIA Tegra Security co-processor 8*a0c70244SSvyatoslav Ryhel 9*a0c70244SSvyatoslav Ryhelmaintainers: 10*a0c70244SSvyatoslav Ryhel - Svyatoslav Ryhel <clamor95@gmail.com> 11*a0c70244SSvyatoslav Ryhel - Thierry Reding <thierry.reding@gmail.com> 12*a0c70244SSvyatoslav Ryhel 13*a0c70244SSvyatoslav Ryheldescription: Tegra Security co-processor, an embedded security processor used 14*a0c70244SSvyatoslav Ryhel mainly to manage the HDCP encryption and keys on the HDMI link. 15*a0c70244SSvyatoslav Ryhel 16*a0c70244SSvyatoslav Ryhelproperties: 17*a0c70244SSvyatoslav Ryhel compatible: 18*a0c70244SSvyatoslav Ryhel oneOf: 19*a0c70244SSvyatoslav Ryhel - enum: 20*a0c70244SSvyatoslav Ryhel - nvidia,tegra114-tsec 21*a0c70244SSvyatoslav Ryhel - nvidia,tegra124-tsec 22*a0c70244SSvyatoslav Ryhel - nvidia,tegra210-tsec 23*a0c70244SSvyatoslav Ryhel 24*a0c70244SSvyatoslav Ryhel - items: 25*a0c70244SSvyatoslav Ryhel - const: nvidia,tegra132-tsec 26*a0c70244SSvyatoslav Ryhel - const: nvidia,tegra124-tsec 27*a0c70244SSvyatoslav Ryhel 28*a0c70244SSvyatoslav Ryhel reg: 29*a0c70244SSvyatoslav Ryhel maxItems: 1 30*a0c70244SSvyatoslav Ryhel 31*a0c70244SSvyatoslav Ryhel interrupts: 32*a0c70244SSvyatoslav Ryhel maxItems: 1 33*a0c70244SSvyatoslav Ryhel 34*a0c70244SSvyatoslav Ryhel clocks: 35*a0c70244SSvyatoslav Ryhel maxItems: 1 36*a0c70244SSvyatoslav Ryhel 37*a0c70244SSvyatoslav Ryhel resets: 38*a0c70244SSvyatoslav Ryhel maxItems: 1 39*a0c70244SSvyatoslav Ryhel 40*a0c70244SSvyatoslav Ryhel iommus: 41*a0c70244SSvyatoslav Ryhel maxItems: 1 42*a0c70244SSvyatoslav Ryhel 43*a0c70244SSvyatoslav Ryhel operating-points-v2: true 44*a0c70244SSvyatoslav Ryhel 45*a0c70244SSvyatoslav Ryhel power-domains: 46*a0c70244SSvyatoslav Ryhel maxItems: 1 47*a0c70244SSvyatoslav Ryhel 48*a0c70244SSvyatoslav RyheladditionalProperties: false 49*a0c70244SSvyatoslav Ryhel 50*a0c70244SSvyatoslav Ryhelrequired: 51*a0c70244SSvyatoslav Ryhel - compatible 52*a0c70244SSvyatoslav Ryhel - reg 53*a0c70244SSvyatoslav Ryhel - interrupts 54*a0c70244SSvyatoslav Ryhel - clocks 55*a0c70244SSvyatoslav Ryhel - resets 56*a0c70244SSvyatoslav Ryhel 57*a0c70244SSvyatoslav Ryhelexamples: 58*a0c70244SSvyatoslav Ryhel - | 59*a0c70244SSvyatoslav Ryhel #include <dt-bindings/clock/tegra114-car.h> 60*a0c70244SSvyatoslav Ryhel #include <dt-bindings/interrupt-controller/arm-gic.h> 61*a0c70244SSvyatoslav Ryhel 62*a0c70244SSvyatoslav Ryhel tsec@54500000 { 63*a0c70244SSvyatoslav Ryhel compatible = "nvidia,tegra114-tsec"; 64*a0c70244SSvyatoslav Ryhel reg = <0x54500000 0x00040000>; 65*a0c70244SSvyatoslav Ryhel interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 66*a0c70244SSvyatoslav Ryhel clocks = <&tegra_car TEGRA114_CLK_TSEC>; 67*a0c70244SSvyatoslav Ryhel resets = <&tegra_car TEGRA114_CLK_TSEC>; 68*a0c70244SSvyatoslav Ryhel }; 69