xref: /linux/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-dp.yaml (revision 6f17ab9a63e670bd62a287f95e3982f99eafd77e) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-dp.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip DW DisplayPort Transmitter
8
9maintainers:
10  - Andy Yan <andy.yan@rock-chips.com>
11
12description: |
13  The Rockchip RK3588 SoC integrates the Synopsys DesignWare DPTX controller
14  which is compliant with the DisplayPort Specification Version 1.4 with the
15  following features:
16
17  * DisplayPort 1.4a
18  * Main Link: 1/2/4 lanes
19  * Main Link Support 1.62Gbps, 2.7Gbps, 5.4Gbps and 8.1Gbps
20  * AUX channel 1Mbps
21  * Single Stream Transport(SST)
22  * Multistream Transport (MST)
23  * Type-C support (alternate mode)
24  * HDCP 2.2, HDCP 1.3
25  * Supports up to 8/10 bits per color component
26  * Supports RBG, YCbCr4:4:4, YCbCr4:2:2, YCbCr4:2:0
27  * Pixel clock up to 594MHz
28  * I2S, SPDIF audio interface
29
30allOf:
31  - $ref: /schemas/sound/dai-common.yaml#
32
33properties:
34  compatible:
35    enum:
36      - rockchip,rk3588-dp
37
38  reg:
39    maxItems: 1
40
41  interrupts:
42    maxItems: 1
43
44  clocks:
45    items:
46      - description: Peripheral/APB bus clock
47      - description: DisplayPort AUX clock
48      - description: HDCP clock
49      - description: I2S interface clock
50      - description: SPDIF interfce clock
51
52  clock-names:
53    items:
54      - const: apb
55      - const: aux
56      - const: hdcp
57      - const: i2s
58      - const: spdif
59
60  phys:
61    maxItems: 1
62
63  ports:
64    $ref: /schemas/graph.yaml#/properties/ports
65
66    properties:
67      port@0:
68        $ref: /schemas/graph.yaml#/properties/port
69        description: Video port for RGB/YUV input.
70
71      port@1:
72        $ref: /schemas/graph.yaml#/properties/port
73        description: Video port for DP output.
74
75    required:
76      - port@0
77      - port@1
78
79  power-domains:
80    maxItems: 1
81
82  resets:
83    maxItems: 1
84
85  "#sound-dai-cells":
86    const: 0
87
88required:
89  - compatible
90  - reg
91  - clocks
92  - clock-names
93  - interrupts
94  - phys
95  - ports
96  - resets
97
98unevaluatedProperties: false
99
100examples:
101  - |
102    #include <dt-bindings/clock/rockchip,rk3588-cru.h>
103    #include <dt-bindings/phy/phy.h>
104    #include <dt-bindings/interrupt-controller/arm-gic.h>
105    #include <dt-bindings/interrupt-controller/irq.h>
106    #include <dt-bindings/power/rk3588-power.h>
107    #include <dt-bindings/reset/rockchip,rk3588-cru.h>
108
109    soc {
110      #address-cells = <2>;
111      #size-cells = <2>;
112
113      dp@fde50000 {
114        compatible = "rockchip,rk3588-dp";
115        reg = <0x0 0xfde50000 0x0 0x4000>;
116        interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>;
117        clocks = <&cru PCLK_DP0>, <&cru CLK_AUX16M_0>,
118        <&cru CLK_DP0>, <&cru MCLK_I2S4_8CH_TX>,
119        <&cru MCLK_SPDIF2_DP0>;
120        clock-names = "apb", "aux", "hdcp", "i2s", "spdif";
121        assigned-clocks = <&cru CLK_AUX16M_0>;
122        assigned-clock-rates = <16000000>;
123        resets = <&cru SRST_DP0>;
124        phys = <&usbdp_phy0 PHY_TYPE_DP>;
125        power-domains = <&power RK3588_PD_VO0>;
126        #sound-dai-cells = <0>;
127
128
129        ports {
130          #address-cells = <1>;
131          #size-cells = <0>;
132
133          port@0 {
134            reg = <0>;
135
136            dp0_in_vp2: endpoint {
137              remote-endpoint = <&vp2_out_dp0>;
138            };
139          };
140
141          port@1 {
142            reg = <1>;
143
144            dp0_out_con0: endpoint {
145              remote-endpoint = <&dp_con0_in>;
146            };
147          };
148        };
149      };
150    };
151