xref: /linux/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml (revision eb01fe7abbe2d0b38824d2a93fdb4cc3eaf2ccc1) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/renesas,rzg2l-du.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas RZ/G2L Display Unit (DU)
8
9maintainers:
10  - Biju Das <biju.das.jz@bp.renesas.com>
11  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
12
13description: |
14  These DT bindings describe the Display Unit embedded in the Renesas RZ/G2L
15  and RZ/V2L SoCs.
16
17properties:
18  compatible:
19    oneOf:
20      - enum:
21          - renesas,r9a07g044-du # RZ/G2{L,LC}
22      - items:
23          - enum:
24              - renesas,r9a07g054-du    # RZ/V2L
25          - const: renesas,r9a07g044-du # RZ/G2L fallback
26
27  reg:
28    maxItems: 1
29
30  interrupts:
31    maxItems: 1
32
33  clocks:
34    items:
35      - description: Main clock
36      - description: Register access clock
37      - description: Video clock
38
39  clock-names:
40    items:
41      - const: aclk
42      - const: pclk
43      - const: vclk
44
45  resets:
46    maxItems: 1
47
48  power-domains:
49    maxItems: 1
50
51  ports:
52    $ref: /schemas/graph.yaml#/properties/ports
53    description: |
54      The connections to the DU output video ports are modeled using the OF
55      graph bindings. The number of ports and their assignment are
56      model-dependent. Each port shall have a single endpoint.
57
58    patternProperties:
59      "^port@[0-1]$":
60        $ref: /schemas/graph.yaml#/properties/port
61        unevaluatedProperties: false
62
63    required:
64      - port@0
65
66    unevaluatedProperties: false
67
68  renesas,vsps:
69    $ref: /schemas/types.yaml#/definitions/phandle-array
70    items:
71      items:
72        - description: phandle to VSP instance that serves the DU channel
73        - description: Channel index identifying the LIF instance in that VSP
74    description:
75      A list of phandle and channel index tuples to the VSPs that handle the
76      memory interfaces for the DU channels.
77
78required:
79  - compatible
80  - reg
81  - interrupts
82  - clocks
83  - clock-names
84  - resets
85  - power-domains
86  - ports
87  - renesas,vsps
88
89additionalProperties: false
90
91examples:
92  # RZ/G2L DU
93  - |
94    #include <dt-bindings/clock/r9a07g044-cpg.h>
95    #include <dt-bindings/interrupt-controller/arm-gic.h>
96
97    display@10890000 {
98        compatible = "renesas,r9a07g044-du";
99        reg = <0x10890000 0x10000>;
100        interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
101        clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
102                 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
103                 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
104        clock-names = "aclk", "pclk", "vclk";
105        resets = <&cpg R9A07G044_LCDC_RESET_N>;
106        power-domains = <&cpg>;
107
108        renesas,vsps = <&vspd0 0>;
109
110        ports {
111            #address-cells = <1>;
112            #size-cells = <0>;
113
114            port@0 {
115                reg = <0>;
116                endpoint {
117                    remote-endpoint = <&dsi0_in>;
118                };
119            };
120            port@1 {
121                reg = <1>;
122            };
123        };
124    };
125
126...
127