xref: /linux/Documentation/devicetree/bindings/display/panel/sharp,lq079l1sx01.yaml (revision 84318277d6334c6981ab326d4acc87c6a6ddc9b8)
1*16c5b1a6SSvyatoslav Ryhel# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*16c5b1a6SSvyatoslav Ryhel%YAML 1.2
3*16c5b1a6SSvyatoslav Ryhel---
4*16c5b1a6SSvyatoslav Ryhel$id: http://devicetree.org/schemas/display/panel/sharp,lq079l1sx01.yaml#
5*16c5b1a6SSvyatoslav Ryhel$schema: http://devicetree.org/meta-schemas/core.yaml#
6*16c5b1a6SSvyatoslav Ryhel
7*16c5b1a6SSvyatoslav Ryheltitle: Sharp Microelectronics 7.9" WQXGA TFT LCD panel
8*16c5b1a6SSvyatoslav Ryhel
9*16c5b1a6SSvyatoslav Ryhelmaintainers:
10*16c5b1a6SSvyatoslav Ryhel  - Svyatoslav Ryhel <clamor95@gmail.com>
11*16c5b1a6SSvyatoslav Ryhel
12*16c5b1a6SSvyatoslav Ryheldescription: >
13*16c5b1a6SSvyatoslav Ryhel  This panel requires a dual-channel DSI host to operate and it supports
14*16c5b1a6SSvyatoslav Ryhel  only left-right split mode, where each channel drives the left or right
15*16c5b1a6SSvyatoslav Ryhel  half of the screen and only video mode.
16*16c5b1a6SSvyatoslav Ryhel
17*16c5b1a6SSvyatoslav Ryhel  Each of the DSI channels controls a separate DSI peripheral.
18*16c5b1a6SSvyatoslav Ryhel  The peripheral driven by the first link (DSI-LINK1), left one, is
19*16c5b1a6SSvyatoslav Ryhel  considered the primary peripheral and controls the device.
20*16c5b1a6SSvyatoslav Ryhel
21*16c5b1a6SSvyatoslav RyhelallOf:
22*16c5b1a6SSvyatoslav Ryhel  - $ref: panel-common-dual.yaml#
23*16c5b1a6SSvyatoslav Ryhel
24*16c5b1a6SSvyatoslav Ryhelproperties:
25*16c5b1a6SSvyatoslav Ryhel  compatible:
26*16c5b1a6SSvyatoslav Ryhel    const: sharp,lq079l1sx01
27*16c5b1a6SSvyatoslav Ryhel
28*16c5b1a6SSvyatoslav Ryhel  reg:
29*16c5b1a6SSvyatoslav Ryhel    maxItems: 1
30*16c5b1a6SSvyatoslav Ryhel
31*16c5b1a6SSvyatoslav Ryhel  avdd-supply:
32*16c5b1a6SSvyatoslav Ryhel    description: regulator that supplies the analog voltage
33*16c5b1a6SSvyatoslav Ryhel
34*16c5b1a6SSvyatoslav Ryhel  vddio-supply:
35*16c5b1a6SSvyatoslav Ryhel    description: regulator that supplies the I/O voltage
36*16c5b1a6SSvyatoslav Ryhel
37*16c5b1a6SSvyatoslav Ryhel  vsp-supply:
38*16c5b1a6SSvyatoslav Ryhel    description: positive boost supply regulator
39*16c5b1a6SSvyatoslav Ryhel
40*16c5b1a6SSvyatoslav Ryhel  vsn-supply:
41*16c5b1a6SSvyatoslav Ryhel    description: negative boost supply regulator
42*16c5b1a6SSvyatoslav Ryhel
43*16c5b1a6SSvyatoslav Ryhel  reset-gpios:
44*16c5b1a6SSvyatoslav Ryhel    maxItems: 1
45*16c5b1a6SSvyatoslav Ryhel
46*16c5b1a6SSvyatoslav Ryhel  backlight: true
47*16c5b1a6SSvyatoslav Ryhel  ports: true
48*16c5b1a6SSvyatoslav Ryhel
49*16c5b1a6SSvyatoslav Ryhelrequired:
50*16c5b1a6SSvyatoslav Ryhel  - compatible
51*16c5b1a6SSvyatoslav Ryhel  - reg
52*16c5b1a6SSvyatoslav Ryhel  - avdd-supply
53*16c5b1a6SSvyatoslav Ryhel  - vddio-supply
54*16c5b1a6SSvyatoslav Ryhel  - ports
55*16c5b1a6SSvyatoslav Ryhel
56*16c5b1a6SSvyatoslav RyheladditionalProperties: false
57*16c5b1a6SSvyatoslav Ryhel
58*16c5b1a6SSvyatoslav Ryhelexamples:
59*16c5b1a6SSvyatoslav Ryhel  - |
60*16c5b1a6SSvyatoslav Ryhel    #include <dt-bindings/gpio/gpio.h>
61*16c5b1a6SSvyatoslav Ryhel
62*16c5b1a6SSvyatoslav Ryhel    dsi {
63*16c5b1a6SSvyatoslav Ryhel        #address-cells = <1>;
64*16c5b1a6SSvyatoslav Ryhel        #size-cells = <0>;
65*16c5b1a6SSvyatoslav Ryhel
66*16c5b1a6SSvyatoslav Ryhel        panel@0 {
67*16c5b1a6SSvyatoslav Ryhel            compatible = "sharp,lq079l1sx01";
68*16c5b1a6SSvyatoslav Ryhel            reg = <0>;
69*16c5b1a6SSvyatoslav Ryhel
70*16c5b1a6SSvyatoslav Ryhel            reset-gpios = <&gpio 59 GPIO_ACTIVE_LOW>;
71*16c5b1a6SSvyatoslav Ryhel
72*16c5b1a6SSvyatoslav Ryhel            avdd-supply = <&avdd_lcd>;
73*16c5b1a6SSvyatoslav Ryhel            vddio-supply = <&vdd_lcd_io>;
74*16c5b1a6SSvyatoslav Ryhel            vsp-supply = <&vsp_5v5_lcd>;
75*16c5b1a6SSvyatoslav Ryhel            vsn-supply = <&vsn_5v5_lcd>;
76*16c5b1a6SSvyatoslav Ryhel
77*16c5b1a6SSvyatoslav Ryhel            backlight = <&backlight>;
78*16c5b1a6SSvyatoslav Ryhel
79*16c5b1a6SSvyatoslav Ryhel            ports {
80*16c5b1a6SSvyatoslav Ryhel                #address-cells = <1>;
81*16c5b1a6SSvyatoslav Ryhel                #size-cells = <0>;
82*16c5b1a6SSvyatoslav Ryhel
83*16c5b1a6SSvyatoslav Ryhel                port@0 {
84*16c5b1a6SSvyatoslav Ryhel                    reg = <0>;
85*16c5b1a6SSvyatoslav Ryhel                    panel_in0: endpoint {
86*16c5b1a6SSvyatoslav Ryhel                        remote-endpoint = <&dsi0_out>;
87*16c5b1a6SSvyatoslav Ryhel                    };
88*16c5b1a6SSvyatoslav Ryhel                };
89*16c5b1a6SSvyatoslav Ryhel
90*16c5b1a6SSvyatoslav Ryhel                port@1 {
91*16c5b1a6SSvyatoslav Ryhel                    reg = <1>;
92*16c5b1a6SSvyatoslav Ryhel                    panel_in1: endpoint {
93*16c5b1a6SSvyatoslav Ryhel                        remote-endpoint = <&dsi1_out>;
94*16c5b1a6SSvyatoslav Ryhel                    };
95*16c5b1a6SSvyatoslav Ryhel                };
96*16c5b1a6SSvyatoslav Ryhel            };
97*16c5b1a6SSvyatoslav Ryhel        };
98*16c5b1a6SSvyatoslav Ryhel    };
99*16c5b1a6SSvyatoslav Ryhel...
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