xref: /linux/Documentation/devicetree/bindings/display/msm/qcom,sm8250-mdss.yaml (revision fd7d598270724cc787982ea48bbe17ad383a8b7f) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sm8250-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM8250 Display MDSS
8
9maintainers:
10  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11
12description:
13  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15  bindings of MDSS are mentioned for SM8250 target.
16
17$ref: /schemas/display/msm/mdss-common.yaml#
18
19properties:
20  compatible:
21    const: qcom,sm8250-mdss
22
23  clocks:
24    items:
25      - description: Display AHB clock from gcc
26      - description: Display hf axi clock
27      - description: Display sf axi clock
28      - description: Display core clock
29
30  clock-names:
31    items:
32      - const: iface
33      - const: bus
34      - const: nrt_bus
35      - const: core
36
37  iommus:
38    maxItems: 1
39
40  interconnects:
41    maxItems: 2
42
43  interconnect-names:
44    maxItems: 2
45
46patternProperties:
47  "^display-controller@[0-9a-f]+$":
48    type: object
49    additionalProperties: true
50
51    properties:
52      compatible:
53        const: qcom,sm8250-dpu
54
55  "^dsi@[0-9a-f]+$":
56    type: object
57    additionalProperties: true
58
59    properties:
60      compatible:
61        items:
62          - const: qcom,sm8250-dsi-ctrl
63          - const: qcom,mdss-dsi-ctrl
64
65  "^phy@[0-9a-f]+$":
66    type: object
67    additionalProperties: true
68
69    properties:
70      compatible:
71        const: qcom,dsi-phy-7nm
72
73required:
74  - compatible
75
76unevaluatedProperties: false
77
78examples:
79  - |
80    #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
81    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
82    #include <dt-bindings/clock/qcom,rpmh.h>
83    #include <dt-bindings/interrupt-controller/arm-gic.h>
84    #include <dt-bindings/interconnect/qcom,sm8250.h>
85    #include <dt-bindings/power/qcom,rpmhpd.h>
86
87    display-subsystem@ae00000 {
88        compatible = "qcom,sm8250-mdss";
89        reg = <0x0ae00000 0x1000>;
90        reg-names = "mdss";
91
92        interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
93                        <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
94        interconnect-names = "mdp0-mem", "mdp1-mem";
95
96        power-domains = <&dispcc MDSS_GDSC>;
97
98        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
99                 <&gcc GCC_DISP_HF_AXI_CLK>,
100                 <&gcc GCC_DISP_SF_AXI_CLK>,
101                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
102        clock-names = "iface", "bus", "nrt_bus", "core";
103
104        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
105        interrupt-controller;
106        #interrupt-cells = <1>;
107
108        iommus = <&apps_smmu 0x820 0x402>;
109
110        #address-cells = <1>;
111        #size-cells = <1>;
112        ranges;
113
114        display-controller@ae01000 {
115            compatible = "qcom,sm8250-dpu";
116            reg = <0x0ae01000 0x8f000>,
117                  <0x0aeb0000 0x2008>;
118            reg-names = "mdp", "vbif";
119
120            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
121                     <&gcc GCC_DISP_HF_AXI_CLK>,
122                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
123                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
124            clock-names = "iface", "bus", "core", "vsync";
125
126            assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
127            assigned-clock-rates = <19200000>;
128
129            operating-points-v2 = <&mdp_opp_table>;
130            power-domains = <&rpmhpd RPMHPD_MMCX>;
131
132            interrupt-parent = <&mdss>;
133            interrupts = <0>;
134
135            ports {
136                #address-cells = <1>;
137                #size-cells = <0>;
138
139                port@0 {
140                    reg = <0>;
141                    dpu_intf1_out: endpoint {
142                        remote-endpoint = <&dsi0_in>;
143                    };
144                };
145
146                port@1 {
147                    reg = <1>;
148                    dpu_intf2_out: endpoint {
149                        remote-endpoint = <&dsi1_in>;
150                    };
151                };
152            };
153
154            mdp_opp_table: opp-table {
155                compatible = "operating-points-v2";
156
157                opp-200000000 {
158                    opp-hz = /bits/ 64 <200000000>;
159                    required-opps = <&rpmhpd_opp_low_svs>;
160                };
161
162                opp-300000000 {
163                    opp-hz = /bits/ 64 <300000000>;
164                    required-opps = <&rpmhpd_opp_svs>;
165                };
166
167                opp-345000000 {
168                    opp-hz = /bits/ 64 <345000000>;
169                    required-opps = <&rpmhpd_opp_svs_l1>;
170                };
171
172                opp-460000000 {
173                    opp-hz = /bits/ 64 <460000000>;
174                    required-opps = <&rpmhpd_opp_nom>;
175                };
176            };
177        };
178
179        dsi@ae94000 {
180            compatible = "qcom,sm8250-dsi-ctrl", "qcom,mdss-dsi-ctrl";
181            reg = <0x0ae94000 0x400>;
182            reg-names = "dsi_ctrl";
183
184            interrupt-parent = <&mdss>;
185            interrupts = <4>;
186
187            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
188                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
189                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
190                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
191                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
192                     <&gcc GCC_DISP_HF_AXI_CLK>;
193            clock-names = "byte",
194                          "byte_intf",
195                          "pixel",
196                          "core",
197                          "iface",
198                          "bus";
199
200            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
201                              <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
202            assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
203
204            operating-points-v2 = <&dsi_opp_table>;
205            power-domains = <&rpmhpd RPMHPD_MMCX>;
206
207            phys = <&dsi0_phy>;
208            phy-names = "dsi";
209
210            #address-cells = <1>;
211            #size-cells = <0>;
212
213            ports {
214                #address-cells = <1>;
215                #size-cells = <0>;
216
217                port@0 {
218                    reg = <0>;
219                    dsi0_in: endpoint {
220                        remote-endpoint = <&dpu_intf1_out>;
221                    };
222                };
223
224                port@1 {
225                    reg = <1>;
226                    dsi0_out: endpoint {
227                    };
228                };
229            };
230
231            dsi_opp_table: opp-table {
232                compatible = "operating-points-v2";
233
234                opp-187500000 {
235                    opp-hz = /bits/ 64 <187500000>;
236                    required-opps = <&rpmhpd_opp_low_svs>;
237                };
238
239                opp-300000000 {
240                    opp-hz = /bits/ 64 <300000000>;
241                    required-opps = <&rpmhpd_opp_svs>;
242                };
243
244                opp-358000000 {
245                    opp-hz = /bits/ 64 <358000000>;
246                    required-opps = <&rpmhpd_opp_svs_l1>;
247                };
248            };
249        };
250
251        dsi0_phy: phy@ae94400 {
252            compatible = "qcom,dsi-phy-7nm";
253            reg = <0x0ae94400 0x200>,
254                  <0x0ae94600 0x280>,
255                  <0x0ae94900 0x260>;
256            reg-names = "dsi_phy",
257                        "dsi_phy_lane",
258                        "dsi_pll";
259
260            #clock-cells = <1>;
261            #phy-cells = <0>;
262
263            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
264                     <&rpmhcc RPMH_CXO_CLK>;
265            clock-names = "iface", "ref";
266            vdds-supply = <&vreg_dsi_phy>;
267        };
268
269        dsi@ae96000 {
270            compatible = "qcom,sm8250-dsi-ctrl", "qcom,mdss-dsi-ctrl";
271            reg = <0x0ae96000 0x400>;
272            reg-names = "dsi_ctrl";
273
274            interrupt-parent = <&mdss>;
275            interrupts = <5>;
276
277            clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
278                     <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
279                     <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
280                     <&dispcc DISP_CC_MDSS_ESC1_CLK>,
281                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
282                     <&gcc GCC_DISP_HF_AXI_CLK>;
283            clock-names = "byte",
284                          "byte_intf",
285                          "pixel",
286                          "core",
287                          "iface",
288                          "bus";
289
290            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
291                              <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
292            assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
293
294            operating-points-v2 = <&dsi_opp_table>;
295            power-domains = <&rpmhpd RPMHPD_MMCX>;
296
297            phys = <&dsi1_phy>;
298            phy-names = "dsi";
299
300            #address-cells = <1>;
301            #size-cells = <0>;
302
303            ports {
304                #address-cells = <1>;
305                #size-cells = <0>;
306
307                port@0 {
308                    reg = <0>;
309                    dsi1_in: endpoint {
310                        remote-endpoint = <&dpu_intf2_out>;
311                    };
312                };
313
314                port@1 {
315                    reg = <1>;
316                    dsi1_out: endpoint {
317                    };
318                };
319            };
320        };
321
322        dsi1_phy: phy@ae96400 {
323            compatible = "qcom,dsi-phy-7nm";
324            reg = <0x0ae96400 0x200>,
325                  <0x0ae96600 0x280>,
326                  <0x0ae96900 0x260>;
327            reg-names = "dsi_phy",
328                        "dsi_phy_lane",
329                        "dsi_pll";
330
331            #clock-cells = <1>;
332            #phy-cells = <0>;
333
334            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
335                     <&rpmhcc RPMH_CXO_CLK>;
336            clock-names = "iface", "ref";
337            vdds-supply = <&vreg_dsi_phy>;
338        };
339    };
340...
341