xref: /linux/Documentation/devicetree/bindings/display/msm/qcom,sm7150-mdss.yaml (revision 6f17ab9a63e670bd62a287f95e3982f99eafd77e) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sm7150-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM7150 Display MDSS
8
9maintainers:
10  - Danila Tikhonov <danila@jiaxyga.com>
11
12description:
13  SM7150 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14  DPU display controller, DSI and DP interfaces etc.
15
16$ref: /schemas/display/msm/mdss-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,sm7150-mdss
21
22  clocks:
23    items:
24      - description: Display ahb clock from gcc
25      - description: Display hf axi clock
26      - description: Display sf axi clock
27      - description: Display core clock
28
29  clock-names:
30    items:
31      - const: iface
32      - const: bus
33      - const: nrt_bus
34      - const: core
35
36  iommus:
37    maxItems: 1
38
39  interconnects:
40    items:
41      - description: Interconnect path from mdp0 port to the data bus
42      - description: Interconnect path from mdp1 port to the data bus
43      - description: Interconnect path from CPU to the reg bus
44
45  interconnect-names:
46    items:
47      - const: mdp0-mem
48      - const: mdp1-mem
49      - const: cpu-cfg
50
51patternProperties:
52  "^display-controller@[0-9a-f]+$":
53    type: object
54    additionalProperties: true
55    properties:
56      compatible:
57        const: qcom,sm7150-dpu
58
59  "^displayport-controller@[0-9a-f]+$":
60    type: object
61    additionalProperties: true
62    properties:
63      compatible:
64        contains:
65          const: qcom,sm7150-dp
66
67  "^dsi@[0-9a-f]+$":
68    type: object
69    additionalProperties: true
70    properties:
71      compatible:
72        items:
73          - const: qcom,sm7150-dsi-ctrl
74          - const: qcom,mdss-dsi-ctrl
75
76  "^phy@[0-9a-f]+$":
77    type: object
78    additionalProperties: true
79    properties:
80      compatible:
81        const: qcom,dsi-phy-10nm
82
83required:
84  - compatible
85
86unevaluatedProperties: false
87
88examples:
89  - |
90    #include <dt-bindings/clock/qcom,rpmh.h>
91    #include <dt-bindings/interconnect/qcom,icc.h>
92    #include <dt-bindings/interconnect/qcom,sm7150-rpmh.h>
93    #include <dt-bindings/interrupt-controller/arm-gic.h>
94    #include <dt-bindings/power/qcom,rpmhpd.h>
95
96    display-subsystem@ae00000 {
97        compatible = "qcom,sm7150-mdss";
98        reg = <0x0ae00000 0x1000>;
99        reg-names = "mdss";
100
101        power-domains = <&dispcc_mdss_gdsc>;
102
103        clocks = <&dispcc_mdss_ahb_clk>,
104                 <&gcc_disp_hf_axi_clk>,
105                 <&gcc_disp_sf_axi_clk>,
106                 <&dispcc_mdss_mdp_clk>;
107        clock-names = "iface",
108                      "bus",
109                      "nrt_bus",
110                      "core";
111
112        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
113        interrupt-controller;
114        #interrupt-cells = <1>;
115
116        interconnects = <&mmss_noc MASTER_MDP_PORT0 QCOM_ICC_TAG_ALWAYS
117                         &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
118                        <&mmss_noc MASTER_MDP_PORT1 QCOM_ICC_TAG_ALWAYS
119                         &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
120                        <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
121                         &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
122        interconnect-names = "mdp0-mem",
123                             "mdp1-mem",
124                             "cpu-cfg";
125
126        iommus = <&apps_smmu 0x800 0x440>;
127
128        #address-cells = <1>;
129        #size-cells = <1>;
130        ranges;
131
132        display-controller@ae01000 {
133            compatible = "qcom,sm7150-dpu";
134            reg = <0x0ae01000 0x8f000>,
135                  <0x0aeb0000 0x2008>;
136            reg-names = "mdp", "vbif";
137
138            clocks = <&gcc_disp_hf_axi_clk>,
139                     <&dispcc_mdss_ahb_clk>,
140                     <&dispcc_mdss_rot_clk>,
141                     <&dispcc_mdss_mdp_lut_clk>,
142                     <&dispcc_mdss_mdp_clk>,
143                     <&dispcc_mdss_vsync_clk>;
144            clock-names = "bus",
145                          "iface",
146                          "rot",
147                          "lut",
148                          "core",
149                          "vsync";
150
151            assigned-clocks = <&dispcc_mdss_vsync_clk>;
152            assigned-clock-rates = <19200000>;
153
154            operating-points-v2 = <&mdp_opp_table>;
155            power-domains = <&rpmhpd RPMHPD_CX>;
156
157            interrupt-parent = <&mdss>;
158            interrupts = <0>;
159
160            ports {
161                #address-cells = <1>;
162                #size-cells = <0>;
163
164                port@0 {
165                    reg = <0>;
166                    dpu_intf1_out: endpoint {
167                        remote-endpoint = <&mdss_dsi0_in>;
168                    };
169                };
170
171                port@1 {
172                    reg = <1>;
173                    dpu_intf2_out: endpoint {
174                        remote-endpoint = <&mdss_dsi1_in>;
175                    };
176                };
177
178                port@2 {
179                    reg = <2>;
180                    dpu_intf0_out: endpoint {
181                        remote-endpoint = <&dp_in>;
182                    };
183                };
184            };
185
186            mdp_opp_table: opp-table {
187                compatible = "operating-points-v2";
188
189                opp-19200000 {
190                    opp-hz = /bits/ 64 <19200000>;
191                    required-opps = <&rpmhpd_opp_min_svs>;
192                };
193
194                opp-200000000 {
195                    opp-hz = /bits/ 64 <200000000>;
196                    required-opps = <&rpmhpd_opp_low_svs>;
197                };
198
199                opp-300000000 {
200                    opp-hz = /bits/ 64 <300000000>;
201                    required-opps = <&rpmhpd_opp_svs>;
202                };
203
204                opp-344000000 {
205                    opp-hz = /bits/ 64 <344000000>;
206                    required-opps = <&rpmhpd_opp_svs_l1>;
207                };
208
209                opp-430000000 {
210                    opp-hz = /bits/ 64 <430000000>;
211                    required-opps = <&rpmhpd_opp_nom>;
212                };
213            };
214        };
215
216        dsi@ae94000 {
217            compatible = "qcom,sm7150-dsi-ctrl",
218                         "qcom,mdss-dsi-ctrl";
219            reg = <0x0ae94000 0x400>;
220            reg-names = "dsi_ctrl";
221
222            interrupt-parent = <&mdss>;
223            interrupts = <4>;
224
225            clocks = <&dispcc_mdss_byte0_clk>,
226                     <&dispcc_mdss_byte0_intf_clk>,
227                     <&dispcc_mdss_pclk0_clk>,
228                     <&dispcc_mdss_esc0_clk>,
229                     <&dispcc_mdss_ahb_clk>,
230                     <&gcc_disp_hf_axi_clk>;
231            clock-names = "byte",
232                          "byte_intf",
233                          "pixel",
234                          "core",
235                          "iface",
236                          "bus";
237
238            assigned-clocks = <&dispcc_mdss_byte0_clk_src>,
239                              <&dispcc_mdss_pclk0_clk_src>;
240            assigned-clock-parents = <&mdss_dsi0_phy 0>,
241                                     <&mdss_dsi0_phy 1>;
242
243            operating-points-v2 = <&dsi_opp_table>;
244            power-domains = <&rpmhpd RPMHPD_CX>;
245
246            phys = <&mdss_dsi0_phy>;
247            phy-names = "dsi";
248
249            #address-cells = <1>;
250            #size-cells = <0>;
251
252            ports {
253                #address-cells = <1>;
254                #size-cells = <0>;
255
256                port@0 {
257                    reg = <0>;
258                    mdss_dsi0_in: endpoint {
259                        remote-endpoint = <&dpu_intf1_out>;
260                    };
261                };
262
263                port@1 {
264                    reg = <1>;
265                    mdss_dsi0_out: endpoint {
266                    };
267                };
268            };
269
270            dsi_opp_table: opp-table {
271                compatible = "operating-points-v2";
272
273                opp-180000000 {
274                    opp-hz = /bits/ 64 <180000000>;
275                    required-opps = <&rpmhpd_opp_low_svs>;
276                };
277
278                opp-275000000 {
279                    opp-hz = /bits/ 64 <275000000>;
280                    required-opps = <&rpmhpd_opp_svs>;
281                };
282
283                opp-358000000 {
284                    opp-hz = /bits/ 64 <358000000>;
285                    required-opps = <&rpmhpd_opp_svs_l1>;
286                };
287            };
288        };
289
290        mdss_dsi0_phy: phy@ae94400 {
291            compatible = "qcom,dsi-phy-10nm";
292            reg = <0x0ae94400 0x200>,
293                  <0x0ae94600 0x280>,
294                  <0x0ae94a00 0x1e0>;
295            reg-names = "dsi_phy",
296                        "dsi_phy_lane",
297                        "dsi_pll";
298
299            #clock-cells = <1>;
300            #phy-cells = <0>;
301
302            clocks = <&dispcc_mdss_ahb_clk>,
303                     <&rpmhcc RPMH_CXO_CLK>;
304            clock-names = "iface", "ref";
305            vdds-supply = <&vdda_mipi_dsi0_pll>;
306        };
307
308        dsi@ae96000 {
309            compatible = "qcom,sm7150-dsi-ctrl",
310                         "qcom,mdss-dsi-ctrl";
311            reg = <0x0ae96000 0x400>;
312            reg-names = "dsi_ctrl";
313
314            interrupt-parent = <&mdss>;
315            interrupts = <5>;
316
317            clocks = <&dispcc_mdss_byte1_clk>,
318                     <&dispcc_mdss_byte1_intf_clk>,
319                     <&dispcc_mdss_pclk1_clk>,
320                     <&dispcc_mdss_esc1_clk>,
321                     <&dispcc_mdss_ahb_clk>,
322                     <&gcc_disp_hf_axi_clk>;
323            clock-names = "byte",
324                          "byte_intf",
325                          "pixel",
326                          "core",
327                          "iface",
328                          "bus";
329
330            assigned-clocks = <&dispcc_mdss_byte1_clk_src>,
331                              <&dispcc_mdss_pclk1_clk_src>;
332            assigned-clock-parents = <&mdss_dsi1_phy 0>,
333                                     <&mdss_dsi1_phy 1>;
334
335            operating-points-v2 = <&dsi_opp_table>;
336            power-domains = <&rpmhpd RPMHPD_CX>;
337
338            phys = <&mdss_dsi1_phy>;
339            phy-names = "dsi";
340
341            #address-cells = <1>;
342            #size-cells = <0>;
343
344            ports {
345                #address-cells = <1>;
346                #size-cells = <0>;
347
348                port@0 {
349                    reg = <0>;
350                    mdss_dsi1_in: endpoint {
351                        remote-endpoint = <&dpu_intf2_out>;
352                    };
353                };
354
355                port@1 {
356                    reg = <1>;
357                    mdss_dsi1_out: endpoint {
358                    };
359                };
360            };
361        };
362
363        mdss_dsi1_phy: phy@ae96400 {
364            compatible = "qcom,dsi-phy-10nm";
365            reg = <0x0ae96400 0x200>,
366                  <0x0ae96600 0x280>,
367                  <0x0ae96a00 0x1e0>;
368            reg-names = "dsi_phy",
369                        "dsi_phy_lane",
370                        "dsi_pll";
371
372            #clock-cells = <1>;
373            #phy-cells = <0>;
374
375            clocks = <&dispcc_mdss_ahb_clk>,
376                     <&rpmhcc RPMH_CXO_CLK>;
377            clock-names = "iface", "ref";
378            vdds-supply = <&vdda_mipi_dsi1_pll>;
379        };
380
381        displayport-controller@ae90000 {
382            compatible = "qcom,sm7150-dp",
383                         "qcom,sm8350-dp";
384            reg = <0xae90000 0x200>,
385                  <0xae90200 0x200>,
386                  <0xae90400 0xc00>,
387                  <0xae91000 0x400>,
388                  <0xae91400 0x400>;
389
390            interrupt-parent = <&mdss>;
391            interrupts = <12>;
392
393            clocks = <&dispcc_mdss_ahb_clk>,
394                     <&dispcc_mdss_dp_aux_clk>,
395                     <&dispcc_mdss_dp_link_clk>,
396                     <&dispcc_mdss_dp_link_intf_clk>,
397                     <&dispcc_mdss_dp_pixel_clk>,
398                     <&dispcc_mdss_dp_pixel1_clk>;
399            clock-names = "core_iface",
400                          "core_aux",
401                          "ctrl_link",
402                          "ctrl_link_iface",
403                          "stream_pixel",
404                          "stream_1_pixel";
405
406            assigned-clocks = <&dispcc_mdss_dp_link_clk_src>,
407                              <&dispcc_mdss_dp_pixel_clk_src>,
408                              <&dispcc_mdss_dp_pixel1_clk_src>;
409            assigned-clock-parents = <&dp_phy 0>,
410                                     <&dp_phy 1>,
411                                     <&dp_phy 1>;
412
413            operating-points-v2 = <&dp_opp_table>;
414            power-domains = <&rpmhpd RPMHPD_CX>;
415
416            phys = <&dp_phy>;
417            phy-names = "dp";
418
419            #sound-dai-cells = <0>;
420
421            ports {
422                #address-cells = <1>;
423                #size-cells = <0>;
424
425                port@0 {
426                    reg = <0>;
427                    dp_in: endpoint {
428                        remote-endpoint = <&dpu_intf0_out>;
429                    };
430                };
431
432                port@1 {
433                    reg = <1>;
434                    dp_out: endpoint {
435                    };
436                };
437            };
438
439            dp_opp_table: opp-table {
440                compatible = "operating-points-v2";
441
442                opp-160000000 {
443                    opp-hz = /bits/ 64 <160000000>;
444                    required-opps = <&rpmhpd_opp_low_svs>;
445                };
446
447                opp-270000000 {
448                    opp-hz = /bits/ 64 <270000000>;
449                    required-opps = <&rpmhpd_opp_svs>;
450                };
451
452                opp-540000000 {
453                    opp-hz = /bits/ 64 <540000000>;
454                    required-opps = <&rpmhpd_opp_svs_l1>;
455                };
456
457                opp-810000000 {
458                    opp-hz = /bits/ 64 <810000000>;
459                    required-opps = <&rpmhpd_opp_nom>;
460                };
461            };
462        };
463    };
464...
465