xref: /linux/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml (revision fd7d598270724cc787982ea48bbe17ad383a8b7f) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sm6375-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM6375 Display MDSS
8
9maintainers:
10  - Konrad Dybcio <konrad.dybcio@linaro.org>
11
12description:
13  SM6375 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
14  like DPU display controller, DSI and DP interfaces etc.
15
16$ref: /schemas/display/msm/mdss-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,sm6375-mdss
21
22  clocks:
23    items:
24      - description: Display AHB clock from gcc
25      - description: Display AHB clock
26      - description: Display core clock
27
28  clock-names:
29    items:
30      - const: iface
31      - const: ahb
32      - const: core
33
34  iommus:
35    maxItems: 1
36
37  interconnects:
38    maxItems: 2
39
40  interconnect-names:
41    maxItems: 2
42
43patternProperties:
44  "^display-controller@[0-9a-f]+$":
45    type: object
46    additionalProperties: true
47
48    properties:
49      compatible:
50        const: qcom,sm6375-dpu
51
52  "^dsi@[0-9a-f]+$":
53    type: object
54    additionalProperties: true
55
56    properties:
57      compatible:
58        items:
59          - const: qcom,sm6375-dsi-ctrl
60          - const: qcom,mdss-dsi-ctrl
61
62  "^phy@[0-9a-f]+$":
63    type: object
64    additionalProperties: true
65
66    properties:
67      compatible:
68        const: qcom,sm6375-dsi-phy-7nm
69
70unevaluatedProperties: false
71
72examples:
73  - |
74    #include <dt-bindings/clock/qcom,rpmcc.h>
75    #include <dt-bindings/clock/qcom,sm6375-gcc.h>
76    #include <dt-bindings/clock/qcom,sm6375-dispcc.h>
77    #include <dt-bindings/interrupt-controller/arm-gic.h>
78    #include <dt-bindings/power/qcom-rpmpd.h>
79
80    display-subsystem@5e00000 {
81        compatible = "qcom,sm6375-mdss";
82        reg = <0x05e00000 0x1000>;
83        reg-names = "mdss";
84
85        power-domains = <&dispcc MDSS_GDSC>;
86
87        clocks = <&gcc GCC_DISP_AHB_CLK>,
88                 <&dispcc DISP_CC_MDSS_AHB_CLK>,
89                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
90        clock-names = "iface", "ahb", "core";
91
92        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
93        interrupt-controller;
94        #interrupt-cells = <1>;
95
96        iommus = <&apps_smmu 0x820 0x2>;
97        #address-cells = <1>;
98        #size-cells = <1>;
99        ranges;
100
101        display-controller@5e01000 {
102            compatible = "qcom,sm6375-dpu";
103            reg = <0x05e01000 0x8e030>,
104                  <0x05eb0000 0x2008>;
105            reg-names = "mdp", "vbif";
106
107            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
108                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
109                     <&dispcc DISP_CC_MDSS_ROT_CLK>,
110                     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
111                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
112                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
113                     <&gcc GCC_DISP_THROTTLE_CORE_CLK>;
114            clock-names = "bus",
115                          "iface",
116                          "rot",
117                          "lut",
118                          "core",
119                          "vsync",
120                          "throttle";
121
122            assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
123            assigned-clock-rates = <19200000>;
124
125            operating-points-v2 = <&mdp_opp_table>;
126            power-domains = <&rpmpd SM6375_VDDCX>;
127
128            interrupt-parent = <&mdss>;
129            interrupts = <0>;
130
131            ports {
132                #address-cells = <1>;
133                #size-cells = <0>;
134
135                port@0 {
136                    reg = <0>;
137                    dpu_intf1_out: endpoint {
138                        remote-endpoint = <&dsi0_in>;
139                    };
140                };
141            };
142        };
143
144        dsi@5e94000 {
145            compatible = "qcom,sm6375-dsi-ctrl", "qcom,mdss-dsi-ctrl";
146            reg = <0x05e94000 0x400>;
147            reg-names = "dsi_ctrl";
148
149            interrupt-parent = <&mdss>;
150            interrupts = <4>;
151
152            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
153                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
154                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
155                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
156                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
157                     <&gcc GCC_DISP_HF_AXI_CLK>;
158            clock-names = "byte",
159                          "byte_intf",
160                          "pixel",
161                          "core",
162                          "iface",
163                          "bus";
164
165            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
166                              <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
167            assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
168
169            operating-points-v2 = <&dsi_opp_table>;
170            power-domains = <&rpmpd SM6375_VDDMX>;
171
172            phys = <&mdss_dsi0_phy>;
173            phy-names = "dsi";
174
175            #address-cells = <1>;
176            #size-cells = <0>;
177
178            ports {
179                #address-cells = <1>;
180                #size-cells = <0>;
181
182                port@0 {
183                    reg = <0>;
184                    dsi0_in: endpoint {
185                        remote-endpoint = <&dpu_intf1_out>;
186                    };
187                };
188
189                port@1 {
190                    reg = <1>;
191                    dsi0_out: endpoint {
192                    };
193                };
194            };
195        };
196
197        mdss_dsi0_phy: phy@5e94400 {
198            compatible = "qcom,sm6375-dsi-phy-7nm";
199            reg = <0x05e94400 0x200>,
200                  <0x05e94600 0x280>,
201                  <0x05e94900 0x264>;
202            reg-names = "dsi_phy",
203                        "dsi_phy_lane",
204                        "dsi_pll";
205
206            #clock-cells = <1>;
207            #phy-cells = <0>;
208
209            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
210                     <&rpmcc RPM_SMD_XO_CLK_SRC>;
211            clock-names = "iface", "ref";
212        };
213    };
214...
215