xref: /linux/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml (revision 5027ec19f1049a07df5b0a37b1f462514cf2724b) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sm6350-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM6350 Display MDSS
8
9maintainers:
10  - Krishna Manikandan <quic_mkrishn@quicinc.com>
11
12description:
13  SM6350 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
14  like DPU display controller, DSI and DP interfaces etc.
15
16$ref: /schemas/display/msm/mdss-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,sm6350-mdss
21
22  clocks:
23    items:
24      - description: Display AHB clock from gcc
25      - description: Display AXI clock from gcc
26      - description: Display core clock
27
28  clock-names:
29    items:
30      - const: iface
31      - const: bus
32      - const: core
33
34  iommus:
35    maxItems: 1
36
37  interconnects:
38    maxItems: 2
39
40  interconnect-names:
41    maxItems: 2
42
43patternProperties:
44  "^display-controller@[0-9a-f]+$":
45    type: object
46    additionalProperties: true
47
48    properties:
49      compatible:
50        const: qcom,sm6350-dpu
51
52  "^dsi@[0-9a-f]+$":
53    type: object
54    additionalProperties: true
55
56    properties:
57      compatible:
58        items:
59          - const: qcom,sm6350-dsi-ctrl
60          - const: qcom,mdss-dsi-ctrl
61
62  "^phy@[0-9a-f]+$":
63    type: object
64    additionalProperties: true
65
66    properties:
67      compatible:
68        const: qcom,dsi-phy-10nm
69
70unevaluatedProperties: false
71
72examples:
73  - |
74    #include <dt-bindings/clock/qcom,dispcc-sm6350.h>
75    #include <dt-bindings/clock/qcom,gcc-sm6350.h>
76    #include <dt-bindings/clock/qcom,rpmh.h>
77    #include <dt-bindings/interrupt-controller/arm-gic.h>
78    #include <dt-bindings/power/qcom-rpmpd.h>
79
80    display-subsystem@ae00000 {
81        compatible = "qcom,sm6350-mdss";
82        reg = <0x0ae00000 0x1000>;
83        reg-names = "mdss";
84
85        power-domains = <&dispcc MDSS_GDSC>;
86
87        clocks = <&gcc GCC_DISP_AHB_CLK>,
88                 <&gcc GCC_DISP_AXI_CLK>,
89                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
90        clock-names = "iface", "bus", "core";
91
92        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
93        interrupt-controller;
94        #interrupt-cells = <1>;
95
96        iommus = <&apps_smmu 0x800 0x2>;
97        #address-cells = <1>;
98        #size-cells = <1>;
99        ranges;
100
101        display-controller@ae01000 {
102            compatible = "qcom,sm6350-dpu";
103            reg = <0x0ae01000 0x8f000>,
104                  <0x0aeb0000 0x2008>;
105            reg-names = "mdp", "vbif";
106
107            clocks = <&gcc GCC_DISP_AXI_CLK>,
108              <&dispcc DISP_CC_MDSS_AHB_CLK>,
109              <&dispcc DISP_CC_MDSS_ROT_CLK>,
110              <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
111              <&dispcc DISP_CC_MDSS_MDP_CLK>,
112              <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
113            clock-names = "bus", "iface", "rot", "lut", "core",
114                    "vsync";
115
116            assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
117                              <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
118                              <&dispcc DISP_CC_MDSS_ROT_CLK>,
119                              <&dispcc DISP_CC_MDSS_AHB_CLK>;
120            assigned-clock-rates = <300000000>,
121                                   <19200000>,
122                                   <19200000>,
123                                   <19200000>;
124
125            interrupt-parent = <&mdss>;
126            interrupts = <0>;
127            operating-points-v2 = <&mdp_opp_table>;
128            power-domains = <&rpmhpd SM6350_CX>;
129
130            ports {
131                #address-cells = <1>;
132                #size-cells = <0>;
133
134                port@0 {
135                    reg = <0>;
136                    dpu_intf1_out: endpoint {
137                        remote-endpoint = <&dsi0_in>;
138                    };
139                };
140            };
141        };
142
143        dsi@ae94000 {
144            compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
145            reg = <0x0ae94000 0x400>;
146            reg-names = "dsi_ctrl";
147
148            interrupt-parent = <&mdss>;
149            interrupts = <4>;
150
151            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
152                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
153                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
154                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
155                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
156                     <&gcc GCC_DISP_AXI_CLK>;
157            clock-names = "byte",
158                          "byte_intf",
159                          "pixel",
160                          "core",
161                          "iface",
162                          "bus";
163
164            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
165                              <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
166            assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
167
168            operating-points-v2 = <&dsi_opp_table>;
169            power-domains = <&rpmhpd SM6350_MX>;
170
171            phys = <&dsi0_phy>;
172            phy-names = "dsi";
173
174            #address-cells = <1>;
175            #size-cells = <0>;
176
177            ports {
178                #address-cells = <1>;
179                #size-cells = <0>;
180
181                port@0 {
182                    reg = <0>;
183                    dsi0_in: endpoint {
184                        remote-endpoint = <&dpu_intf1_out>;
185                    };
186                };
187
188                port@1 {
189                    reg = <1>;
190                    dsi0_out: endpoint {
191                    };
192                };
193            };
194        };
195
196        dsi0_phy: phy@ae94400 {
197            compatible = "qcom,dsi-phy-10nm";
198            reg = <0x0ae94400 0x200>,
199                  <0x0ae94600 0x280>,
200                  <0x0ae94a00 0x1e0>;
201            reg-names = "dsi_phy",
202                        "dsi_phy_lane",
203                        "dsi_pll";
204
205            #clock-cells = <1>;
206            #phy-cells = <0>;
207
208            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>;
209            clock-names = "iface", "ref";
210        };
211    };
212...
213