xref: /linux/Documentation/devicetree/bindings/display/msm/qcom,sm6125-mdss.yaml (revision 4eca0ef49af9b2b0c52ef2b58e045ab34629796b) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sm6125-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM6125 Display MDSS
8
9maintainers:
10  - Marijn Suijten <marijn.suijten@somainline.org>
11
12description:
13  SM6125 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
14  like DPU display controller, DSI and DP interfaces etc.
15
16$ref: /schemas/display/msm/mdss-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,sm6125-mdss
21
22  clocks:
23    items:
24      - description: Display AHB clock from gcc
25      - description: Display AHB clock
26      - description: Display core clock
27
28  clock-names:
29    items:
30      - const: iface
31      - const: ahb
32      - const: core
33
34  iommus:
35    maxItems: 1
36
37  interconnects:
38    maxItems: 2
39
40  interconnect-names:
41    maxItems: 2
42
43patternProperties:
44  "^display-controller@[0-9a-f]+$":
45    type: object
46    additionalProperties: true
47
48    properties:
49      compatible:
50        const: qcom,sm6125-dpu
51
52  "^dsi@[0-9a-f]+$":
53    type: object
54    additionalProperties: true
55
56    properties:
57      compatible:
58        items:
59          - const: qcom,sm6125-dsi-ctrl
60          - const: qcom,mdss-dsi-ctrl
61
62  "^phy@[0-9a-f]+$":
63    type: object
64    additionalProperties: true
65
66    properties:
67      compatible:
68        const: qcom,sm6125-dsi-phy-14nm
69
70unevaluatedProperties: false
71
72examples:
73  - |
74    #include <dt-bindings/clock/qcom,dispcc-sm6125.h>
75    #include <dt-bindings/clock/qcom,gcc-sm6125.h>
76    #include <dt-bindings/clock/qcom,rpmcc.h>
77    #include <dt-bindings/interrupt-controller/arm-gic.h>
78    #include <dt-bindings/power/qcom-rpmpd.h>
79
80    display-subsystem@5e00000 {
81        compatible = "qcom,sm6125-mdss";
82        reg = <0x05e00000 0x1000>;
83        reg-names = "mdss";
84
85        interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
86        interrupt-controller;
87        #interrupt-cells = <1>;
88
89        clocks = <&gcc GCC_DISP_AHB_CLK>,
90                 <&dispcc DISP_CC_MDSS_AHB_CLK>,
91                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
92        clock-names = "iface",
93                      "ahb",
94                      "core";
95
96        power-domains = <&dispcc MDSS_GDSC>;
97
98        iommus = <&apps_smmu 0x400 0x0>;
99
100        #address-cells = <1>;
101        #size-cells = <1>;
102        ranges;
103
104        display-controller@5e01000 {
105            compatible = "qcom,sm6125-dpu";
106            reg = <0x05e01000 0x83208>,
107                  <0x05eb0000 0x2008>;
108            reg-names = "mdp", "vbif";
109
110            interrupt-parent = <&mdss>;
111            interrupts = <0>;
112
113            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
114                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
115                     <&dispcc DISP_CC_MDSS_ROT_CLK>,
116                     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
117                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
118                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
119                     <&gcc GCC_DISP_THROTTLE_CORE_CLK>;
120            clock-names = "bus",
121                          "iface",
122                          "rot",
123                          "lut",
124                          "core",
125                          "vsync",
126                          "throttle";
127            assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
128            assigned-clock-rates = <19200000>;
129
130            operating-points-v2 = <&mdp_opp_table>;
131            power-domains = <&rpmpd SM6125_VDDCX>;
132
133            ports {
134                #address-cells = <1>;
135                #size-cells = <0>;
136
137                port@0 {
138                    reg = <0>;
139                    dpu_intf1_out: endpoint {
140                        remote-endpoint = <&mdss_dsi0_in>;
141                    };
142                };
143            };
144        };
145
146        dsi@5e94000 {
147            compatible = "qcom,sm6125-dsi-ctrl", "qcom,mdss-dsi-ctrl";
148            reg = <0x05e94000 0x400>;
149            reg-names = "dsi_ctrl";
150
151            interrupt-parent = <&mdss>;
152            interrupts = <4>;
153
154            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
155                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
156                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
157                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
158                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
159                     <&gcc GCC_DISP_HF_AXI_CLK>;
160            clock-names = "byte",
161                          "byte_intf",
162                          "pixel",
163                          "core",
164                          "iface",
165                          "bus";
166            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
167                      <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
168            assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
169
170            operating-points-v2 = <&dsi_opp_table>;
171            power-domains = <&rpmpd SM6125_VDDCX>;
172
173            phys = <&mdss_dsi0_phy>;
174            phy-names = "dsi";
175
176            #address-cells = <1>;
177            #size-cells = <0>;
178
179            ports {
180                #address-cells = <1>;
181                #size-cells = <0>;
182
183                port@0 {
184                    reg = <0>;
185                    mdss_dsi0_in: endpoint {
186                        remote-endpoint = <&dpu_intf1_out>;
187                    };
188                };
189
190                port@1 {
191                    reg = <1>;
192                    mdss_dsi0_out: endpoint {
193                    };
194                };
195            };
196        };
197
198        phy@5e94400 {
199            compatible = "qcom,sm6125-dsi-phy-14nm";
200            reg = <0x05e94400 0x100>,
201                  <0x05e94500 0x300>,
202                  <0x05e94800 0x188>;
203            reg-names = "dsi_phy",
204                        "dsi_phy_lane",
205                        "dsi_pll";
206
207            #clock-cells = <1>;
208            #phy-cells = <0>;
209
210            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
211                     <&rpmcc RPM_SMD_XO_CLK_SRC>;
212            clock-names = "iface",
213                          "ref";
214
215            required-opps = <&rpmpd_opp_nom>;
216            power-domains = <&rpmpd SM6125_VDDMX>;
217        };
218    };
219...
220