xref: /linux/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml (revision c5dbf04160005e07e8ca7232a7faa77ab1547ae0) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM6115 Display MDSS
8
9maintainers:
10  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11
12description:
13  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14  sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
15  are mentioned for SM6115 target.
16
17$ref: /schemas/display/msm/mdss-common.yaml#
18
19properties:
20  compatible:
21    const: qcom,sm6115-mdss
22
23  clocks:
24    items:
25      - description: Display AHB clock from gcc
26      - description: Display AXI clock
27      - description: Display core clock
28
29  iommus:
30    maxItems: 2
31
32patternProperties:
33  "^display-controller@[0-9a-f]+$":
34    type: object
35    additionalProperties: true
36
37    properties:
38      compatible:
39        const: qcom,sm6115-dpu
40
41  "^dsi@[0-9a-f]+$":
42    type: object
43    additionalProperties: true
44
45    properties:
46      compatible:
47        oneOf:
48          - items:
49              - const: qcom,sm6115-dsi-ctrl
50              - const: qcom,mdss-dsi-ctrl
51          - description: Old binding, please don't use
52            deprecated: true
53            const: qcom,dsi-ctrl-6g-qcm2290
54
55  "^phy@[0-9a-f]+$":
56    type: object
57    additionalProperties: true
58
59    properties:
60      compatible:
61        const: qcom,dsi-phy-14nm-2290
62
63required:
64  - compatible
65
66unevaluatedProperties: false
67
68examples:
69  - |
70    #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
71    #include <dt-bindings/clock/qcom,gcc-sm6115.h>
72    #include <dt-bindings/clock/qcom,rpmcc.h>
73    #include <dt-bindings/interrupt-controller/arm-gic.h>
74    #include <dt-bindings/power/qcom-rpmpd.h>
75
76    display-subsystem@5e00000 {
77        #address-cells = <1>;
78        #size-cells = <1>;
79        compatible = "qcom,sm6115-mdss";
80        reg = <0x05e00000 0x1000>;
81        reg-names = "mdss";
82        power-domains = <&dispcc MDSS_GDSC>;
83        clocks = <&gcc GCC_DISP_AHB_CLK>,
84                 <&gcc GCC_DISP_HF_AXI_CLK>,
85                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
86
87        interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
88        interrupt-controller;
89        #interrupt-cells = <1>;
90
91        iommus = <&apps_smmu 0x420 0x2>,
92                 <&apps_smmu 0x421 0x0>;
93        ranges;
94
95        display-controller@5e01000 {
96            compatible = "qcom,sm6115-dpu";
97            reg = <0x05e01000 0x8f000>,
98                  <0x05eb0000 0x2008>;
99            reg-names = "mdp", "vbif";
100
101            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
102                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
103                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
104                     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
105                     <&dispcc DISP_CC_MDSS_ROT_CLK>,
106                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
107            clock-names = "bus", "iface", "core", "lut", "rot", "vsync";
108
109            operating-points-v2 = <&mdp_opp_table>;
110            power-domains = <&rpmpd SM6115_VDDCX>;
111
112            interrupt-parent = <&mdss>;
113            interrupts = <0>;
114
115            ports {
116                #address-cells = <1>;
117                #size-cells = <0>;
118
119                port@0 {
120                    reg = <0>;
121                    dpu_intf1_out: endpoint {
122                        remote-endpoint = <&dsi0_in>;
123                    };
124                };
125            };
126        };
127
128        dsi@5e94000 {
129            compatible = "qcom,sm6115-dsi-ctrl", "qcom,mdss-dsi-ctrl";
130            reg = <0x05e94000 0x400>;
131            reg-names = "dsi_ctrl";
132
133            interrupt-parent = <&mdss>;
134            interrupts = <4>;
135
136            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
137                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
138                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
139                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
140                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
141                     <&gcc GCC_DISP_HF_AXI_CLK>;
142            clock-names = "byte",
143                          "byte_intf",
144                          "pixel",
145                          "core",
146                          "iface",
147                          "bus";
148            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
149            assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
150
151            operating-points-v2 = <&dsi_opp_table>;
152            power-domains = <&rpmpd SM6115_VDDCX>;
153            phys = <&dsi0_phy>;
154
155            #address-cells = <1>;
156            #size-cells = <0>;
157
158            ports {
159                #address-cells = <1>;
160                #size-cells = <0>;
161
162                port@0 {
163                    reg = <0>;
164                    dsi0_in: endpoint {
165                        remote-endpoint = <&dpu_intf1_out>;
166                    };
167                };
168
169                port@1 {
170                    reg = <1>;
171                    dsi0_out: endpoint {
172                    };
173                };
174            };
175        };
176
177        dsi0_phy: phy@5e94400 {
178            compatible = "qcom,dsi-phy-14nm-2290";
179            reg = <0x05e94400 0x100>,
180                  <0x05e94500 0x300>,
181                  <0x05e94800 0x188>;
182            reg-names = "dsi_phy",
183                        "dsi_phy_lane",
184                        "dsi_pll";
185
186            #clock-cells = <1>;
187            #phy-cells = <0>;
188
189            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
190            clock-names = "iface", "ref";
191        };
192    };
193...
194