xref: /linux/Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-mdss.yaml (revision fc2d791a43d3880496d1c729b8bd74d2c19cb4e7) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SC8280XP Mobile Display Subsystem
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11
12description:
13  Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates
14  sub-blocks like DPU display controller, DSI and DP interfaces etc.
15
16$ref: /schemas/display/msm/mdss-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,sc8280xp-mdss
21
22  clocks:
23    items:
24      - description: Display AHB clock from gcc
25      - description: Display AHB clock from dispcc
26      - description: Display core clock
27
28  clock-names:
29    items:
30      - const: iface
31      - const: ahb
32      - const: core
33
34patternProperties:
35  "^display-controller@[0-9a-f]+$":
36    type: object
37    additionalProperties: true
38
39    properties:
40      compatible:
41        const: qcom,sc8280xp-dpu
42
43  "^displayport-controller@[0-9a-f]+$":
44    type: object
45    additionalProperties: true
46
47    properties:
48      compatible:
49        enum:
50          - qcom,sc8280xp-dp
51          - qcom,sc8280xp-edp
52
53  "^dsi@[0-9a-f]+$":
54    type: object
55    additionalProperties: true
56    properties:
57      compatible:
58        contains:
59          const: qcom,sc8280xp-dsi-ctrl
60
61  "^phy@[0-9a-f]+$":
62    type: object
63    additionalProperties: true
64    properties:
65      compatible:
66        contains:
67          const: qcom,sc8280xp-dsi-phy-5nm
68
69unevaluatedProperties: false
70
71examples:
72  - |
73    #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
74    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
75    #include <dt-bindings/interrupt-controller/arm-gic.h>
76    #include <dt-bindings/interconnect/qcom,sc8280xp.h>
77    #include <dt-bindings/power/qcom-rpmpd.h>
78
79    display-subsystem@ae00000 {
80        compatible = "qcom,sc8280xp-mdss";
81        reg = <0x0ae00000 0x1000>;
82        reg-names = "mdss";
83
84        power-domains = <&dispcc0 MDSS_GDSC>;
85
86        clocks = <&gcc GCC_DISP_AHB_CLK>,
87                 <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
88                 <&dispcc0 DISP_CC_MDSS_MDP_CLK>;
89        clock-names = "iface",
90                      "ahb",
91                      "core";
92
93        resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
94
95        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
96        interrupt-controller;
97        #interrupt-cells = <1>;
98
99        interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
100                        <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
101        interconnect-names = "mdp0-mem", "mdp1-mem";
102
103        iommus = <&apps_smmu 0x1000 0x402>;
104
105        #address-cells = <1>;
106        #size-cells = <1>;
107        ranges;
108
109        display-controller@ae01000 {
110            compatible = "qcom,sc8280xp-dpu";
111            reg = <0x0ae01000 0x8f000>,
112            <0x0aeb0000 0x2008>;
113            reg-names = "mdp", "vbif";
114
115            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
116                     <&gcc GCC_DISP_SF_AXI_CLK>,
117                     <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
118                     <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,
119                     <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
120                     <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
121            clock-names = "bus",
122                          "nrt_bus",
123                          "iface",
124                          "lut",
125                          "core",
126                          "vsync";
127
128            assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
129            assigned-clock-rates = <19200000>;
130
131            operating-points-v2 = <&mdss0_mdp_opp_table>;
132            power-domains = <&rpmhpd SC8280XP_MMCX>;
133
134            interrupt-parent = <&mdss0>;
135            interrupts = <0>;
136
137            ports {
138                #address-cells = <1>;
139                #size-cells = <0>;
140
141                port@0 {
142                    reg = <0>;
143                    endpoint {
144                        remote-endpoint = <&mdss0_dp0_in>;
145                    };
146                };
147
148                port@1 {
149                    reg = <1>;
150                    dpu_intf1_out: endpoint {
151                        remote-endpoint = <&mdss0_dsi0_in>;
152                    };
153                };
154
155                port@2 {
156                    reg = <2>;
157                    dpu_intf2_out: endpoint {
158                        remote-endpoint = <&mdss0_dsi1_in>;
159                    };
160                };
161
162                port@4 {
163                    reg = <4>;
164                    endpoint {
165                        remote-endpoint = <&mdss0_dp1_in>;
166                    };
167                };
168
169                port@5 {
170                    reg = <5>;
171                    endpoint {
172                        remote-endpoint = <&mdss0_dp3_in>;
173                    };
174                };
175
176                port@6 {
177                    reg = <6>;
178                    endpoint {
179                        remote-endpoint = <&mdss0_dp2_in>;
180                    };
181                };
182            };
183        };
184    };
185...
186