xref: /linux/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml (revision 7f71507851fc7764b36a3221839607d3a45c2025) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sc7280-dpu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display DPU on SC7280
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Neil Armstrong <neil.armstrong@linaro.org>
12  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
13  - Krishna Manikandan <quic_mkrishn@quicinc.com>
14
15$ref: /schemas/display/msm/dpu-common.yaml#
16
17properties:
18  compatible:
19    enum:
20      - qcom,sc7280-dpu
21      - qcom,sc8280xp-dpu
22      - qcom,sm8350-dpu
23      - qcom,sm8450-dpu
24      - qcom,sm8550-dpu
25
26  reg:
27    items:
28      - description: Address offset and size for mdp register set
29      - description: Address offset and size for vbif register set
30
31  reg-names:
32    items:
33      - const: mdp
34      - const: vbif
35
36  clocks:
37    items:
38      - description: Display hf axi clock
39      - description: Display sf axi clock
40      - description: Display ahb clock
41      - description: Display lut clock
42      - description: Display core clock
43      - description: Display vsync clock
44
45  clock-names:
46    items:
47      - const: bus
48      - const: nrt_bus
49      - const: iface
50      - const: lut
51      - const: core
52      - const: vsync
53
54required:
55  - compatible
56  - reg
57  - reg-names
58  - clocks
59  - clock-names
60
61unevaluatedProperties: false
62
63examples:
64  - |
65    #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
66    #include <dt-bindings/clock/qcom,gcc-sc7280.h>
67    #include <dt-bindings/power/qcom-rpmpd.h>
68
69    display-controller@ae01000 {
70        compatible = "qcom,sc7280-dpu";
71        reg = <0x0ae01000 0x8f000>,
72              <0x0aeb0000 0x2008>;
73
74        reg-names = "mdp", "vbif";
75
76        clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
77                 <&gcc GCC_DISP_SF_AXI_CLK>,
78                 <&dispcc DISP_CC_MDSS_AHB_CLK>,
79                 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
80                 <&dispcc DISP_CC_MDSS_MDP_CLK>,
81                 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
82        clock-names = "bus",
83                      "nrt_bus",
84                      "iface",
85                      "lut",
86                      "core",
87                      "vsync";
88
89        interrupt-parent = <&mdss>;
90        interrupts = <0>;
91        power-domains = <&rpmhpd SC7280_CX>;
92        operating-points-v2 = <&mdp_opp_table>;
93
94        ports {
95            #address-cells = <1>;
96            #size-cells = <0>;
97
98            port@0 {
99                reg = <0>;
100                endpoint {
101                    remote-endpoint = <&dsi0_in>;
102                };
103            };
104
105            port@1 {
106                reg = <1>;
107                endpoint {
108                    remote-endpoint = <&edp_in>;
109                };
110            };
111        };
112    };
113...
114