xref: /linux/Documentation/devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml (revision fd7d598270724cc787982ea48bbe17ad383a8b7f) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sc7180-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SC7180 Display MDSS
8
9maintainers:
10  - Krishna Manikandan <quic_mkrishn@quicinc.com>
11
12description:
13  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15  bindings of MDSS are mentioned for SC7180 target.
16
17$ref: /schemas/display/msm/mdss-common.yaml#
18
19properties:
20  compatible:
21    const: qcom,sc7180-mdss
22
23  clocks:
24    items:
25      - description: Display AHB clock from gcc
26      - description: Display AHB clock from dispcc
27      - description: Display core clock
28
29  clock-names:
30    items:
31      - const: iface
32      - const: ahb
33      - const: core
34
35  iommus:
36    maxItems: 1
37
38  interconnects:
39    maxItems: 1
40
41  interconnect-names:
42    maxItems: 1
43
44patternProperties:
45  "^display-controller@[0-9a-f]+$":
46    type: object
47    additionalProperties: true
48
49    properties:
50      compatible:
51        const: qcom,sc7180-dpu
52
53  "^displayport-controller@[0-9a-f]+$":
54    type: object
55    additionalProperties: true
56
57    properties:
58      compatible:
59        const: qcom,sc7180-dp
60
61  "^dsi@[0-9a-f]+$":
62    type: object
63    additionalProperties: true
64
65    properties:
66      compatible:
67        items:
68          - const: qcom,sc7180-dsi-ctrl
69          - const: qcom,mdss-dsi-ctrl
70
71  "^phy@[0-9a-f]+$":
72    type: object
73    additionalProperties: true
74
75    properties:
76      compatible:
77        const: qcom,dsi-phy-10nm
78
79required:
80  - compatible
81
82unevaluatedProperties: false
83
84examples:
85  - |
86    #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
87    #include <dt-bindings/clock/qcom,gcc-sc7180.h>
88    #include <dt-bindings/clock/qcom,rpmh.h>
89    #include <dt-bindings/interrupt-controller/arm-gic.h>
90    #include <dt-bindings/interconnect/qcom,sdm845.h>
91    #include <dt-bindings/power/qcom-rpmpd.h>
92
93    display-subsystem@ae00000 {
94        #address-cells = <1>;
95        #size-cells = <1>;
96        compatible = "qcom,sc7180-mdss";
97        reg = <0xae00000 0x1000>;
98        reg-names = "mdss";
99        power-domains = <&dispcc MDSS_GDSC>;
100        clocks = <&gcc GCC_DISP_AHB_CLK>,
101                 <&dispcc DISP_CC_MDSS_AHB_CLK>,
102                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
103        clock-names = "iface", "ahb", "core";
104
105        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
106        interrupt-controller;
107        #interrupt-cells = <1>;
108
109        interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
110        interconnect-names = "mdp0-mem";
111
112        iommus = <&apps_smmu 0x800 0x2>;
113        ranges;
114
115        display-controller@ae01000 {
116            compatible = "qcom,sc7180-dpu";
117            reg = <0x0ae01000 0x8f000>,
118                  <0x0aeb0000 0x2008>;
119
120            reg-names = "mdp", "vbif";
121
122            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
123                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
124                     <&dispcc DISP_CC_MDSS_ROT_CLK>,
125                     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
126                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
127                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
128            clock-names = "bus", "iface", "rot", "lut", "core",
129                          "vsync";
130
131            interrupt-parent = <&mdss>;
132            interrupts = <0>;
133            power-domains = <&rpmhpd SC7180_CX>;
134            operating-points-v2 = <&mdp_opp_table>;
135
136            ports {
137                #address-cells = <1>;
138                #size-cells = <0>;
139
140                port@0 {
141                    reg = <0>;
142                    dpu_intf1_out: endpoint {
143                        remote-endpoint = <&dsi0_in>;
144                    };
145                };
146
147                port@2 {
148                    reg = <2>;
149                    dpu_intf0_out: endpoint {
150                        remote-endpoint = <&dp_in>;
151                    };
152                };
153            };
154        };
155
156        dsi@ae94000 {
157            compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl";
158            reg = <0x0ae94000 0x400>;
159            reg-names = "dsi_ctrl";
160
161            interrupt-parent = <&mdss>;
162            interrupts = <4>;
163
164            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
165                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
166                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
167                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
168                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
169                     <&gcc GCC_DISP_HF_AXI_CLK>;
170            clock-names = "byte",
171                          "byte_intf",
172                          "pixel",
173                          "core",
174                          "iface",
175                          "bus";
176
177            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
178            assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
179
180            operating-points-v2 = <&dsi_opp_table>;
181            power-domains = <&rpmhpd SC7180_CX>;
182
183            phys = <&dsi_phy>;
184            phy-names = "dsi";
185
186            #address-cells = <1>;
187            #size-cells = <0>;
188
189            ports {
190                #address-cells = <1>;
191                #size-cells = <0>;
192
193                port@0 {
194                    reg = <0>;
195                    dsi0_in: endpoint {
196                        remote-endpoint = <&dpu_intf1_out>;
197                    };
198                };
199
200                port@1 {
201                    reg = <1>;
202                    dsi0_out: endpoint {
203                    };
204                };
205            };
206
207            dsi_opp_table: opp-table {
208                compatible = "operating-points-v2";
209
210                opp-187500000 {
211                    opp-hz = /bits/ 64 <187500000>;
212                    required-opps = <&rpmhpd_opp_low_svs>;
213                };
214
215                opp-300000000 {
216                    opp-hz = /bits/ 64 <300000000>;
217                    required-opps = <&rpmhpd_opp_svs>;
218                };
219
220                opp-358000000 {
221                    opp-hz = /bits/ 64 <358000000>;
222                    required-opps = <&rpmhpd_opp_svs_l1>;
223                };
224            };
225        };
226
227        dsi_phy: phy@ae94400 {
228            compatible = "qcom,dsi-phy-10nm";
229            reg = <0x0ae94400 0x200>,
230                  <0x0ae94600 0x280>,
231                  <0x0ae94a00 0x1e0>;
232            reg-names = "dsi_phy",
233                    "dsi_phy_lane",
234                    "dsi_pll";
235
236            #clock-cells = <1>;
237            #phy-cells = <0>;
238
239            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
240                 <&rpmhcc RPMH_CXO_CLK>;
241            clock-names = "iface", "ref";
242            vdds-supply = <&vreg_dsi_phy>;
243        };
244
245        displayport-controller@ae90000 {
246            compatible = "qcom,sc7180-dp";
247
248            reg = <0xae90000 0x200>,
249                  <0xae90200 0x200>,
250                  <0xae90400 0xc00>,
251                  <0xae91000 0x400>,
252                  <0xae91400 0x400>;
253
254            interrupt-parent = <&mdss>;
255            interrupts = <12>;
256
257            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
258                     <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
259                     <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
260                     <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
261                     <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
262            clock-names = "core_iface", "core_aux", "ctrl_link",
263                          "ctrl_link_iface", "stream_pixel";
264            assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
265                              <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
266            assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
267            phys = <&dp_phy>;
268            phy-names = "dp";
269
270            operating-points-v2 = <&dp_opp_table>;
271            power-domains = <&rpmhpd SC7180_CX>;
272
273            #sound-dai-cells = <0>;
274
275            ports {
276                #address-cells = <1>;
277                #size-cells = <0>;
278                port@0 {
279                    reg = <0>;
280                    dp_in: endpoint {
281                        remote-endpoint = <&dpu_intf0_out>;
282                    };
283                };
284
285                port@1 {
286                    reg = <1>;
287                    dp_out: endpoint { };
288                };
289            };
290
291            dp_opp_table: opp-table {
292                compatible = "operating-points-v2";
293
294                opp-160000000 {
295                    opp-hz = /bits/ 64 <160000000>;
296                    required-opps = <&rpmhpd_opp_low_svs>;
297                };
298
299                opp-270000000 {
300                    opp-hz = /bits/ 64 <270000000>;
301                    required-opps = <&rpmhpd_opp_svs>;
302                };
303
304                opp-540000000 {
305                    opp-hz = /bits/ 64 <540000000>;
306                    required-opps = <&rpmhpd_opp_svs_l1>;
307                };
308
309                opp-810000000 {
310                    opp-hz = /bits/ 64 <810000000>;
311                    required-opps = <&rpmhpd_opp_nom>;
312                };
313            };
314        };
315    };
316...
317