xref: /linux/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml (revision 6f17ab9a63e670bd62a287f95e3982f99eafd77e) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sar2130p-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SAR2130P Display MDSS
8
9maintainers:
10  - Dmitry Baryshkov <lumag@kernel.org>
11
12description:
13  SAR2310P MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14  DPU display controller, DSI and DP interfaces etc.
15
16$ref: /schemas/display/msm/mdss-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,sar2130p-mdss
21
22  clocks:
23    items:
24      - description: Display MDSS AHB
25      - description: Display AHB
26      - description: Display hf AXI
27      - description: Display core
28
29  iommus:
30    maxItems: 1
31
32  interconnects:
33    items:
34      - description: Interconnect path from mdp0 port to the data bus
35      - description: Interconnect path from CPU to the reg bus
36
37  interconnect-names:
38    items:
39      - const: mdp0-mem
40      - const: cpu-cfg
41
42patternProperties:
43  "^display-controller@[0-9a-f]+$":
44    type: object
45    additionalProperties: true
46    properties:
47      compatible:
48        const: qcom,sar2130p-dpu
49
50  "^displayport-controller@[0-9a-f]+$":
51    type: object
52    additionalProperties: true
53    properties:
54      compatible:
55        contains:
56          const: qcom,sar2130p-dp
57
58  "^dsi@[0-9a-f]+$":
59    type: object
60    additionalProperties: true
61    properties:
62      compatible:
63        contains:
64          const: qcom,sar2130p-dsi-ctrl
65
66  "^phy@[0-9a-f]+$":
67    type: object
68    additionalProperties: true
69    properties:
70      compatible:
71        const: qcom,sar2130p-dsi-phy-5nm
72
73required:
74  - compatible
75
76unevaluatedProperties: false
77
78examples:
79  - |
80    #include <dt-bindings/interrupt-controller/arm-gic.h>
81    #include <dt-bindings/power/qcom,rpmhpd.h>
82    #include <dt-bindings/phy/phy-qcom-qmp.h>
83
84    display-subsystem@ae00000 {
85        compatible = "qcom,sar2130p-mdss";
86        reg = <0x0ae00000 0x1000>;
87        reg-names = "mdss";
88
89        interconnects = <&mmss_noc_master_mdp &mc_virt_slave_ebi1>,
90                        <&gem_noc_master_appss_proc &config_noc_slave_display_cfg>;
91        interconnect-names = "mdp0-mem", "cpu-cfg";
92
93        resets = <&dispcc_disp_cc_mdss_core_bcr>;
94
95        power-domains = <&dispcc_mdss_gdsc>;
96
97        clocks = <&dispcc_disp_cc_mdss_ahb_clk>,
98                 <&gcc_gcc_disp_ahb_clk>,
99                 <&gcc_gcc_disp_hf_axi_clk>,
100                 <&dispcc_disp_cc_mdss_mdp_clk>;
101        clock-names = "iface", "bus", "nrt_bus", "core";
102
103        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
104        interrupt-controller;
105        #interrupt-cells = <1>;
106
107        iommus = <&apps_smmu 0x1c00 0x2>;
108
109        #address-cells = <1>;
110        #size-cells = <1>;
111        ranges;
112
113        display-controller@ae01000 {
114            compatible = "qcom,sar2130p-dpu";
115            reg = <0x0ae01000 0x8f000>,
116                  <0x0aeb0000 0x2008>;
117            reg-names = "mdp", "vbif";
118
119            clocks = <&gcc_gcc_disp_ahb_clk>,
120                     <&gcc_gcc_disp_hf_axi_clk>,
121                     <&dispcc_disp_cc_mdss_ahb_clk>,
122                     <&dispcc_disp_cc_mdss_mdp_lut_clk>,
123                     <&dispcc_disp_cc_mdss_mdp_clk>,
124                     <&dispcc_disp_cc_mdss_vsync_clk>;
125            clock-names = "bus",
126                          "nrt_bus",
127                          "iface",
128                          "lut",
129                          "core",
130                          "vsync";
131
132            assigned-clocks = <&dispcc_disp_cc_mdss_vsync_clk>;
133            assigned-clock-rates = <19200000>;
134
135            operating-points-v2 = <&mdp_opp_table>;
136            power-domains = <&rpmhpd RPMHPD_MMCX>;
137
138            interrupt-parent = <&mdss>;
139            interrupts = <0>;
140
141            ports {
142                #address-cells = <1>;
143                #size-cells = <0>;
144
145                port@0 {
146                    reg = <0>;
147
148                    dpu_intf0_out: endpoint {
149                        remote-endpoint = <&mdss_dp0_in>;
150                    };
151                };
152
153                port@1 {
154                    reg = <1>;
155
156                    dpu_intf1_out: endpoint {
157                        remote-endpoint = <&mdss_dsi0_in>;
158                    };
159                };
160
161                port@2 {
162                    reg = <2>;
163
164                    dpu_intf2_out: endpoint {
165                        remote-endpoint = <&mdss_dsi1_in>;
166                    };
167                };
168            };
169
170            mdp_opp_table: opp-table {
171                compatible = "operating-points-v2";
172
173                opp-200000000 {
174                    opp-hz = /bits/ 64 <200000000>;
175                    required-opps = <&rpmhpd_opp_low_svs>;
176                };
177
178                opp-325000000 {
179                    opp-hz = /bits/ 64 <325000000>;
180                    required-opps = <&rpmhpd_opp_svs>;
181                };
182
183                opp-375000000 {
184                    opp-hz = /bits/ 64 <375000000>;
185                    required-opps = <&rpmhpd_opp_svs_l1>;
186                };
187
188                opp-514000000 {
189                    opp-hz = /bits/ 64 <514000000>;
190                    required-opps = <&rpmhpd_opp_nom>;
191                };
192            };
193        };
194
195        displayport-controller@ae90000 {
196            compatible = "qcom,sar2130p-dp",
197                         "qcom,sm8350-dp";
198            reg = <0xae90000 0x200>,
199                  <0xae90200 0x200>,
200                  <0xae90400 0xc00>,
201                  <0xae91000 0x400>,
202                  <0xae91400 0x400>;
203
204            interrupt-parent = <&mdss>;
205            interrupts = <12>;
206            clocks = <&dispcc_disp_cc_mdss_ahb_clk>,
207                     <&dispcc_disp_cc_mdss_dptx0_aux_clk>,
208                     <&dispcc_disp_cc_mdss_dptx0_link_clk>,
209                     <&dispcc_disp_cc_mdss_dptx0_link_intf_clk>,
210                     <&dispcc_disp_cc_mdss_dptx0_pixel0_clk>,
211                     <&dispcc_disp_cc_mdss_dptx0_pixel1_clk>;
212            clock-names = "core_iface",
213                          "core_aux",
214                          "ctrl_link",
215                          "ctrl_link_iface",
216                          "stream_pixel",
217                          "stream_1_pixel";
218
219            assigned-clocks = <&dispcc_disp_cc_mdss_dptx0_link_clk_src>,
220                              <&dispcc_disp_cc_mdss_dptx0_pixel0_clk_src>,
221                              <&dispcc_disp_cc_mdss_dptx0_pixel1_clk_src>;
222            assigned-clock-parents = <&usb_dp_qmpphy_QMP_USB43DP_DP_LINK_CLK>,
223                                     <&usb_dp_qmpphy_QMP_USB43DP_DP_VCO_DIV_CLK>,
224                                     <&usb_dp_qmpphy_QMP_USB43DP_DP_VCO_DIV_CLK>;
225
226            phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
227            phy-names = "dp";
228
229            #sound-dai-cells = <0>;
230
231            operating-points-v2 = <&dp_opp_table>;
232            power-domains = <&rpmhpd RPMHPD_MMCX>;
233
234            ports {
235                #address-cells = <1>;
236                #size-cells = <0>;
237
238                port@0 {
239                    reg = <0>;
240                    mdss_dp0_in: endpoint {
241                        remote-endpoint = <&dpu_intf0_out>;
242                    };
243                };
244
245                port@1 {
246                    reg = <1>;
247                    mdss_dp0_out: endpoint {
248                        remote-endpoint = <&usb_dp_qmpphy_dp_in>;
249                    };
250                };
251        };
252
253        dp_opp_table: opp-table {
254                compatible = "operating-points-v2";
255
256                opp-162000000 {
257                    opp-hz = /bits/ 64 <162000000>;
258                    required-opps = <&rpmhpd_opp_low_svs_d1>;
259                };
260
261                opp-270000000 {
262                    opp-hz = /bits/ 64 <270000000>;
263                    required-opps = <&rpmhpd_opp_low_svs>;
264                };
265
266                opp-540000000 {
267                    opp-hz = /bits/ 64 <540000000>;
268                    required-opps = <&rpmhpd_opp_svs_l1>;
269                };
270
271                opp-810000000 {
272                    opp-hz = /bits/ 64 <810000000>;
273                    required-opps = <&rpmhpd_opp_nom>;
274                };
275            };
276        };
277
278        dsi@ae94000 {
279            compatible = "qcom,sar2130p-dsi-ctrl",
280                         "qcom,mdss-dsi-ctrl";
281            reg = <0x0ae94000 0x400>;
282            reg-names = "dsi_ctrl";
283
284            interrupt-parent = <&mdss>;
285            interrupts = <4>;
286
287            clocks = <&dispcc_disp_cc_mdss_byte0_clk>,
288                     <&dispcc_disp_cc_mdss_byte0_intf_clk>,
289                     <&dispcc_disp_cc_mdss_pclk0_clk>,
290                     <&dispcc_disp_cc_mdss_esc0_clk>,
291                     <&dispcc_disp_cc_mdss_ahb_clk>,
292                     <&gcc_gcc_disp_hf_axi_clk>;
293            clock-names = "byte",
294                          "byte_intf",
295                          "pixel",
296                          "core",
297                          "iface",
298                          "bus";
299
300            assigned-clocks = <&dispcc_disp_cc_mdss_byte0_clk_src>,
301                              <&dispcc_disp_cc_mdss_pclk0_clk_src>;
302            assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
303
304            operating-points-v2 = <&dsi_opp_table>;
305            power-domains = <&rpmhpd RPMHPD_MMCX>;
306
307            phys = <&mdss_dsi0_phy>;
308            phy-names = "dsi";
309
310            #address-cells = <1>;
311            #size-cells = <0>;
312
313            ports {
314                #address-cells = <1>;
315                #size-cells = <0>;
316
317                port@0 {
318                    reg = <0>;
319
320                    mdss_dsi0_in: endpoint {
321                        remote-endpoint = <&dpu_intf1_out>;
322                    };
323                };
324
325                port@1 {
326                    reg = <1>;
327
328                    mdss_dsi0_out: endpoint {
329                    };
330                };
331            };
332
333            dsi_opp_table: opp-table {
334                compatible = "operating-points-v2";
335
336                opp-187500000 {
337                    opp-hz = /bits/ 64 <187500000>;
338                    required-opps = <&rpmhpd_opp_low_svs>;
339                };
340
341                opp-300000000 {
342                    opp-hz = /bits/ 64 <300000000>;
343                    required-opps = <&rpmhpd_opp_svs>;
344                };
345
346                opp-358000000 {
347                    opp-hz = /bits/ 64 <358000000>;
348                    required-opps = <&rpmhpd_opp_svs_l1>;
349                };
350            };
351        };
352
353        mdss_dsi0_phy: phy@ae94400 {
354            compatible = "qcom,sar2130p-dsi-phy-5nm";
355            reg = <0x0ae95000 0x200>,
356                  <0x0ae95200 0x280>,
357                  <0x0ae95500 0x400>;
358            reg-names = "dsi_phy",
359                        "dsi_phy_lane",
360                        "dsi_pll";
361
362            #clock-cells = <1>;
363            #phy-cells = <0>;
364
365            clocks = <&dispcc_disp_cc_mdss_ahb_clk>,
366                     <&rpmhcc_rpmh_cxo_clk>;
367            clock-names = "iface", "ref";
368        };
369
370        dsi@ae96000 {
371            compatible = "qcom,sar2130p-dsi-ctrl",
372                         "qcom,mdss-dsi-ctrl";
373            reg = <0x0ae96000 0x400>;
374            reg-names = "dsi_ctrl";
375
376            interrupt-parent = <&mdss>;
377            interrupts = <5>;
378
379            clocks = <&dispcc_disp_cc_mdss_byte1_clk>,
380                     <&dispcc_disp_cc_mdss_byte1_intf_clk>,
381                     <&dispcc_disp_cc_mdss_pclk1_clk>,
382                     <&dispcc_disp_cc_mdss_esc1_clk>,
383                     <&dispcc_disp_cc_mdss_ahb_clk>,
384                     <&gcc_gcc_disp_hf_axi_clk>;
385            clock-names = "byte",
386                          "byte_intf",
387                          "pixel",
388                          "core",
389                          "iface",
390                          "bus";
391
392            assigned-clocks = <&dispcc_disp_cc_mdss_byte1_clk_src>,
393                              <&dispcc_disp_cc_mdss_pclk1_clk_src>;
394            assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
395
396            operating-points-v2 = <&dsi_opp_table>;
397            power-domains = <&rpmhpd RPMHPD_MMCX>;
398
399            phys = <&mdss_dsi1_phy>;
400            phy-names = "dsi";
401
402            #address-cells = <1>;
403            #size-cells = <0>;
404
405            ports {
406                #address-cells = <1>;
407                #size-cells = <0>;
408
409                port@0 {
410                    reg = <0>;
411
412                    mdss_dsi1_in: endpoint {
413                        remote-endpoint = <&dpu_intf2_out>;
414                    };
415                };
416
417                port@1 {
418                    reg = <1>;
419
420                    mdss_dsi1_out: endpoint {
421                    };
422                };
423            };
424        };
425
426        mdss_dsi1_phy: phy@ae97000 {
427            compatible = "qcom,sar2130p-dsi-phy-5nm";
428            reg = <0x0ae97000 0x200>,
429                  <0x0ae97200 0x280>,
430                  <0x0ae97500 0x400>;
431            reg-names = "dsi_phy",
432                        "dsi_phy_lane",
433                        "dsi_pll";
434
435            #clock-cells = <1>;
436            #phy-cells = <0>;
437
438            clocks = <&dispcc_disp_cc_mdss_ahb_clk>,
439                     <&rpmhcc_rpmh_cxo_clk>;
440            clock-names = "iface", "ref";
441        };
442    };
443...
444