xref: /linux/Documentation/devicetree/bindings/display/msm/qcom,msm8998-mdss.yaml (revision 981368e1440b76f68b1ac8f5fb14e739f80ecc4e) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,msm8998-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm MSM8998 Display MDSS
8
9maintainers:
10  - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
11
12description:
13  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15  bindings of MDSS are mentioned for MSM8998 target.
16
17$ref: /schemas/display/msm/mdss-common.yaml#
18
19properties:
20  compatible:
21    const: qcom,msm8998-mdss
22
23  clocks:
24    items:
25      - description: Display AHB clock
26      - description: Display AXI clock
27      - description: Display core clock
28
29  clock-names:
30    items:
31      - const: iface
32      - const: bus
33      - const: core
34
35  iommus:
36    maxItems: 1
37
38patternProperties:
39  "^display-controller@[0-9a-f]+$":
40    type: object
41    properties:
42      compatible:
43        const: qcom,msm8998-dpu
44
45  "^dsi@[0-9a-f]+$":
46    type: object
47    properties:
48      compatible:
49        items:
50          - const: qcom,msm8998-dsi-ctrl
51          - const: qcom,mdss-dsi-ctrl
52
53  "^phy@[0-9a-f]+$":
54    type: object
55    properties:
56      compatible:
57        const: qcom,dsi-phy-10nm-8998
58
59required:
60  - compatible
61
62unevaluatedProperties: false
63
64examples:
65  - |
66    #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
67    #include <dt-bindings/clock/qcom,rpmcc.h>
68    #include <dt-bindings/interrupt-controller/arm-gic.h>
69    #include <dt-bindings/power/qcom-rpmpd.h>
70
71    display-subsystem@c900000 {
72        compatible = "qcom,msm8998-mdss";
73        reg = <0x0c900000 0x1000>;
74        reg-names = "mdss";
75
76        clocks = <&mmcc MDSS_AHB_CLK>,
77                 <&mmcc MDSS_AXI_CLK>,
78                 <&mmcc MDSS_MDP_CLK>;
79        clock-names = "iface", "bus", "core";
80
81        #address-cells = <1>;
82        #interrupt-cells = <1>;
83        #size-cells = <1>;
84
85        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
86        interrupt-controller;
87        iommus = <&mmss_smmu 0>;
88
89        power-domains = <&mmcc MDSS_GDSC>;
90        ranges;
91
92        display-controller@c901000 {
93            compatible = "qcom,msm8998-dpu";
94            reg = <0x0c901000 0x8f000>,
95                  <0x0c9a8e00 0xf0>,
96                  <0x0c9b0000 0x2008>,
97                  <0x0c9b8000 0x1040>;
98            reg-names = "mdp", "regdma", "vbif", "vbif_nrt";
99
100            clocks = <&mmcc MDSS_AHB_CLK>,
101                     <&mmcc MDSS_AXI_CLK>,
102                     <&mmcc MNOC_AHB_CLK>,
103                     <&mmcc MDSS_MDP_CLK>,
104                     <&mmcc MDSS_VSYNC_CLK>;
105            clock-names = "iface", "bus", "mnoc", "core", "vsync";
106
107            interrupt-parent = <&mdss>;
108            interrupts = <0>;
109            operating-points-v2 = <&mdp_opp_table>;
110            power-domains = <&rpmpd MSM8998_VDDMX>;
111
112            ports {
113                #address-cells = <1>;
114                #size-cells = <0>;
115
116                port@0 {
117                    reg = <0>;
118                    dpu_intf1_out: endpoint {
119                        remote-endpoint = <&dsi0_in>;
120                    };
121                };
122
123                port@1 {
124                    reg = <1>;
125                    dpu_intf2_out: endpoint {
126                        remote-endpoint = <&dsi1_in>;
127                    };
128                };
129            };
130        };
131
132        dsi@c994000 {
133            compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
134            reg = <0x0c994000 0x400>;
135            reg-names = "dsi_ctrl";
136
137            interrupt-parent = <&mdss>;
138            interrupts = <4>;
139
140            clocks = <&mmcc MDSS_BYTE0_CLK>,
141                     <&mmcc MDSS_BYTE0_INTF_CLK>,
142                     <&mmcc MDSS_PCLK0_CLK>,
143                     <&mmcc MDSS_ESC0_CLK>,
144                     <&mmcc MDSS_AHB_CLK>,
145                     <&mmcc MDSS_AXI_CLK>;
146            clock-names = "byte",
147                          "byte_intf",
148                          "pixel",
149                          "core",
150                          "iface",
151                          "bus";
152            assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
153            assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
154
155            operating-points-v2 = <&dsi_opp_table>;
156            power-domains = <&rpmpd MSM8998_VDDCX>;
157
158            phys = <&dsi0_phy>;
159            phy-names = "dsi";
160
161            #address-cells = <1>;
162            #size-cells = <0>;
163
164            ports {
165                #address-cells = <1>;
166                #size-cells = <0>;
167
168                port@0 {
169                    reg = <0>;
170                    dsi0_in: endpoint {
171                        remote-endpoint = <&dpu_intf1_out>;
172                    };
173                };
174
175                port@1 {
176                    reg = <1>;
177                    dsi0_out: endpoint {
178                    };
179                };
180            };
181        };
182
183        dsi0_phy: phy@c994400 {
184            compatible = "qcom,dsi-phy-10nm-8998";
185            reg = <0x0c994400 0x200>,
186                  <0x0c994600 0x280>,
187                  <0x0c994a00 0x1e0>;
188            reg-names = "dsi_phy",
189                        "dsi_phy_lane",
190                        "dsi_pll";
191
192            #clock-cells = <1>;
193            #phy-cells = <0>;
194
195            clocks = <&mmcc MDSS_AHB_CLK>,
196                     <&rpmcc RPM_SMD_XO_CLK_SRC>;
197            clock-names = "iface", "ref";
198
199            vdds-supply = <&pm8998_l1>;
200        };
201
202        dsi@c996000 {
203            compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
204            reg = <0x0c996000 0x400>;
205            reg-names = "dsi_ctrl";
206
207            interrupt-parent = <&mdss>;
208            interrupts = <5>;
209
210            clocks = <&mmcc MDSS_BYTE1_CLK>,
211                     <&mmcc MDSS_BYTE1_INTF_CLK>,
212                     <&mmcc MDSS_PCLK1_CLK>,
213                     <&mmcc MDSS_ESC1_CLK>,
214                     <&mmcc MDSS_AHB_CLK>,
215                     <&mmcc MDSS_AXI_CLK>;
216            clock-names = "byte",
217                          "byte_intf",
218                          "pixel",
219                          "core",
220                          "iface",
221                          "bus";
222            assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
223            assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
224
225            operating-points-v2 = <&dsi_opp_table>;
226            power-domains = <&rpmpd MSM8998_VDDCX>;
227
228            phys = <&dsi1_phy>;
229            phy-names = "dsi";
230
231            #address-cells = <1>;
232            #size-cells = <0>;
233
234            ports {
235                #address-cells = <1>;
236                #size-cells = <0>;
237
238                port@0 {
239                    reg = <0>;
240                    dsi1_in: endpoint {
241                        remote-endpoint = <&dpu_intf2_out>;
242                    };
243                };
244
245                port@1 {
246                    reg = <1>;
247                    dsi1_out: endpoint {
248                    };
249                };
250            };
251        };
252
253        dsi1_phy: phy@c996400 {
254            compatible = "qcom,dsi-phy-10nm-8998";
255            reg = <0x0c996400 0x200>,
256                  <0x0c996600 0x280>,
257                  <0x0c996a00 0x10e>;
258            reg-names = "dsi_phy",
259                        "dsi_phy_lane",
260                        "dsi_pll";
261
262            #clock-cells = <1>;
263            #phy-cells = <0>;
264
265            clocks = <&mmcc MDSS_AHB_CLK>,
266                     <&rpmcc RPM_SMD_XO_CLK_SRC>;
267            clock-names = "iface", "ref";
268
269            vdds-supply = <&pm8998_l1>;
270        };
271    };
272...
273