1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/msm/qcom,msm8998-mdss.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm MSM8998 Display MDSS 8 9maintainers: 10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> 11 12description: 13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates 14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree 15 bindings of MDSS are mentioned for MSM8998 target. 16 17$ref: /schemas/display/msm/mdss-common.yaml# 18 19properties: 20 compatible: 21 items: 22 - const: qcom,msm8998-mdss 23 24 clocks: 25 items: 26 - description: Display AHB clock 27 - description: Display AXI clock 28 - description: Display core clock 29 30 clock-names: 31 items: 32 - const: iface 33 - const: bus 34 - const: core 35 36 iommus: 37 maxItems: 1 38 39patternProperties: 40 "^display-controller@[0-9a-f]+$": 41 type: object 42 properties: 43 compatible: 44 const: qcom,msm8998-dpu 45 46 "^dsi@[0-9a-f]+$": 47 type: object 48 properties: 49 compatible: 50 const: qcom,mdss-dsi-ctrl 51 52 "^phy@[0-9a-f]+$": 53 type: object 54 properties: 55 compatible: 56 const: qcom,dsi-phy-10nm-8998 57 58unevaluatedProperties: false 59 60examples: 61 - | 62 #include <dt-bindings/clock/qcom,mmcc-msm8998.h> 63 #include <dt-bindings/clock/qcom,rpmcc.h> 64 #include <dt-bindings/interrupt-controller/arm-gic.h> 65 #include <dt-bindings/power/qcom-rpmpd.h> 66 67 display-subsystem@c900000 { 68 compatible = "qcom,msm8998-mdss"; 69 reg = <0x0c900000 0x1000>; 70 reg-names = "mdss"; 71 72 clocks = <&mmcc MDSS_AHB_CLK>, 73 <&mmcc MDSS_AXI_CLK>, 74 <&mmcc MDSS_MDP_CLK>; 75 clock-names = "iface", "bus", "core"; 76 77 #address-cells = <1>; 78 #interrupt-cells = <1>; 79 #size-cells = <1>; 80 81 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 82 interrupt-controller; 83 iommus = <&mmss_smmu 0>; 84 85 power-domains = <&mmcc MDSS_GDSC>; 86 ranges; 87 88 display-controller@c901000 { 89 compatible = "qcom,msm8998-dpu"; 90 reg = <0x0c901000 0x8f000>, 91 <0x0c9a8e00 0xf0>, 92 <0x0c9b0000 0x2008>, 93 <0x0c9b8000 0x1040>; 94 reg-names = "mdp", "regdma", "vbif", "vbif_nrt"; 95 96 clocks = <&mmcc MDSS_AHB_CLK>, 97 <&mmcc MDSS_AXI_CLK>, 98 <&mmcc MNOC_AHB_CLK>, 99 <&mmcc MDSS_MDP_CLK>, 100 <&mmcc MDSS_VSYNC_CLK>; 101 clock-names = "iface", "bus", "mnoc", "core", "vsync"; 102 103 interrupt-parent = <&mdss>; 104 interrupts = <0>; 105 operating-points-v2 = <&mdp_opp_table>; 106 power-domains = <&rpmpd MSM8998_VDDMX>; 107 108 ports { 109 #address-cells = <1>; 110 #size-cells = <0>; 111 112 port@0 { 113 reg = <0>; 114 dpu_intf1_out: endpoint { 115 remote-endpoint = <&dsi0_in>; 116 }; 117 }; 118 119 port@1 { 120 reg = <1>; 121 dpu_intf2_out: endpoint { 122 remote-endpoint = <&dsi1_in>; 123 }; 124 }; 125 }; 126 }; 127 128 dsi@c994000 { 129 compatible = "qcom,mdss-dsi-ctrl"; 130 reg = <0x0c994000 0x400>; 131 reg-names = "dsi_ctrl"; 132 133 interrupt-parent = <&mdss>; 134 interrupts = <4>; 135 136 clocks = <&mmcc MDSS_BYTE0_CLK>, 137 <&mmcc MDSS_BYTE0_INTF_CLK>, 138 <&mmcc MDSS_PCLK0_CLK>, 139 <&mmcc MDSS_ESC0_CLK>, 140 <&mmcc MDSS_AHB_CLK>, 141 <&mmcc MDSS_AXI_CLK>; 142 clock-names = "byte", 143 "byte_intf", 144 "pixel", 145 "core", 146 "iface", 147 "bus"; 148 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; 149 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 150 151 operating-points-v2 = <&dsi_opp_table>; 152 power-domains = <&rpmpd MSM8998_VDDCX>; 153 154 phys = <&dsi0_phy>; 155 phy-names = "dsi"; 156 157 #address-cells = <1>; 158 #size-cells = <0>; 159 160 ports { 161 #address-cells = <1>; 162 #size-cells = <0>; 163 164 port@0 { 165 reg = <0>; 166 dsi0_in: endpoint { 167 remote-endpoint = <&dpu_intf1_out>; 168 }; 169 }; 170 171 port@1 { 172 reg = <1>; 173 dsi0_out: endpoint { 174 }; 175 }; 176 }; 177 }; 178 179 dsi0_phy: phy@c994400 { 180 compatible = "qcom,dsi-phy-10nm-8998"; 181 reg = <0x0c994400 0x200>, 182 <0x0c994600 0x280>, 183 <0x0c994a00 0x1e0>; 184 reg-names = "dsi_phy", 185 "dsi_phy_lane", 186 "dsi_pll"; 187 188 #clock-cells = <1>; 189 #phy-cells = <0>; 190 191 clocks = <&mmcc MDSS_AHB_CLK>, 192 <&rpmcc RPM_SMD_XO_CLK_SRC>; 193 clock-names = "iface", "ref"; 194 195 vdds-supply = <&pm8998_l1>; 196 }; 197 198 dsi@c996000 { 199 compatible = "qcom,mdss-dsi-ctrl"; 200 reg = <0x0c996000 0x400>; 201 reg-names = "dsi_ctrl"; 202 203 interrupt-parent = <&mdss>; 204 interrupts = <5>; 205 206 clocks = <&mmcc MDSS_BYTE1_CLK>, 207 <&mmcc MDSS_BYTE1_INTF_CLK>, 208 <&mmcc MDSS_PCLK1_CLK>, 209 <&mmcc MDSS_ESC1_CLK>, 210 <&mmcc MDSS_AHB_CLK>, 211 <&mmcc MDSS_AXI_CLK>; 212 clock-names = "byte", 213 "byte_intf", 214 "pixel", 215 "core", 216 "iface", 217 "bus"; 218 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; 219 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; 220 221 operating-points-v2 = <&dsi_opp_table>; 222 power-domains = <&rpmpd MSM8998_VDDCX>; 223 224 phys = <&dsi1_phy>; 225 phy-names = "dsi"; 226 227 #address-cells = <1>; 228 #size-cells = <0>; 229 230 ports { 231 #address-cells = <1>; 232 #size-cells = <0>; 233 234 port@0 { 235 reg = <0>; 236 dsi1_in: endpoint { 237 remote-endpoint = <&dpu_intf2_out>; 238 }; 239 }; 240 241 port@1 { 242 reg = <1>; 243 dsi1_out: endpoint { 244 }; 245 }; 246 }; 247 }; 248 249 dsi1_phy: phy@c996400 { 250 compatible = "qcom,dsi-phy-10nm-8998"; 251 reg = <0x0c996400 0x200>, 252 <0x0c996600 0x280>, 253 <0x0c996a00 0x10e>; 254 reg-names = "dsi_phy", 255 "dsi_phy_lane", 256 "dsi_pll"; 257 258 #clock-cells = <1>; 259 #phy-cells = <0>; 260 261 clocks = <&mmcc MDSS_AHB_CLK>, 262 <&rpmcc RPM_SMD_XO_CLK_SRC>; 263 clock-names = "iface", "ref"; 264 265 vdds-supply = <&pm8998_l1>; 266 }; 267 }; 268... 269