xref: /linux/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml (revision e7e86d7697c6ed1dbbde18d7185c35b6967945ed) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Mobile Display SubSystem (MDSS)
8
9maintainers:
10  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11  - Rob Clark <robdclark@gmail.com>
12
13description:
14  This is the bindings documentation for the Mobile Display Subsystem(MDSS) that
15  encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc.
16
17properties:
18  $nodename:
19    pattern: "^display-subsystem@[0-9a-f]+$"
20
21  compatible:
22    enum:
23      - qcom,mdss
24
25  reg:
26    minItems: 2
27    maxItems: 3
28
29  reg-names:
30    minItems: 2
31    items:
32      - const: mdss_phys
33      - const: vbif_phys
34      - const: vbif_nrt_phys
35
36  interrupts:
37    maxItems: 1
38
39  interrupt-controller: true
40
41  "#interrupt-cells":
42    const: 1
43
44  power-domains:
45    maxItems: 1
46    description: |
47      The MDSS power domain provided by GCC
48
49  clocks:
50    oneOf:
51      - minItems: 3
52        items:
53          - description: Display abh clock
54          - description: Display axi clock
55          - description: Display vsync clock
56          - description: Display core clock
57      - minItems: 1
58        items:
59          - description: Display abh clock
60          - description: Display core clock
61
62  clock-names:
63    oneOf:
64      - minItems: 3
65        items:
66          - const: iface
67          - const: bus
68          - const: vsync
69          - const: core
70      - minItems: 1
71        items:
72          - const: iface
73          - const: core
74
75  "#address-cells":
76    const: 1
77
78  "#size-cells":
79    const: 1
80
81  ranges: true
82
83  resets:
84    items:
85      - description: MDSS_CORE reset
86
87  interconnects:
88    minItems: 1
89    items:
90      - description: Interconnect path from mdp0 (or a single mdp) port to the data bus
91      - description: Interconnect path from CPU to the reg bus
92
93  interconnect-names:
94    minItems: 1
95    items:
96      - const: mdp0-mem
97      - const: cpu-cfg
98
99required:
100  - compatible
101  - reg
102  - reg-names
103  - interrupts
104  - interrupt-controller
105  - "#interrupt-cells"
106  - power-domains
107  - clocks
108  - clock-names
109  - "#address-cells"
110  - "#size-cells"
111  - ranges
112
113patternProperties:
114  "^display-controller@[1-9a-f][0-9a-f]*$":
115    type: object
116    additionalProperties: true
117    properties:
118      compatible:
119        contains:
120          const: qcom,mdp5
121
122  "^dsi@[1-9a-f][0-9a-f]*$":
123    type: object
124    additionalProperties: true
125    properties:
126      compatible:
127        contains:
128          const: qcom,mdss-dsi-ctrl
129
130  "^phy@[1-9a-f][0-9a-f]*$":
131    type: object
132    additionalProperties: true
133    properties:
134      compatible:
135        enum:
136          - qcom,dsi-phy-14nm
137          - qcom,dsi-phy-14nm-660
138          - qcom,dsi-phy-14nm-8953
139          - qcom,dsi-phy-20nm
140          - qcom,dsi-phy-28nm-8226
141          - qcom,dsi-phy-28nm-8937
142          - qcom,dsi-phy-28nm-hpm
143          - qcom,dsi-phy-28nm-hpm-fam-b
144          - qcom,dsi-phy-28nm-lp
145          - qcom,hdmi-phy-8084
146          - qcom,hdmi-phy-8660
147          - qcom,hdmi-phy-8960
148          - qcom,hdmi-phy-8974
149          - qcom,hdmi-phy-8996
150
151  "^hdmi-tx@[1-9a-f][0-9a-f]*$":
152    type: object
153    additionalProperties: true
154    properties:
155      compatible:
156        enum:
157          - qcom,hdmi-tx-8084
158          - qcom,hdmi-tx-8660
159          - qcom,hdmi-tx-8960
160          - qcom,hdmi-tx-8974
161          - qcom,hdmi-tx-8994
162          - qcom,hdmi-tx-8996
163
164additionalProperties: false
165
166examples:
167  - |
168    #include <dt-bindings/clock/qcom,gcc-msm8916.h>
169    #include <dt-bindings/interrupt-controller/arm-gic.h>
170    display-subsystem@1a00000 {
171        compatible = "qcom,mdss";
172        reg = <0x1a00000 0x1000>,
173              <0x1ac8000 0x3000>;
174        reg-names = "mdss_phys", "vbif_phys";
175
176        power-domains = <&gcc MDSS_GDSC>;
177
178        clocks = <&gcc GCC_MDSS_AHB_CLK>,
179                 <&gcc GCC_MDSS_AXI_CLK>,
180                 <&gcc GCC_MDSS_VSYNC_CLK>;
181        clock-names = "iface",
182                      "bus",
183                      "vsync";
184
185        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
186
187        interrupt-controller;
188        #interrupt-cells = <1>;
189
190        #address-cells = <1>;
191        #size-cells = <1>;
192        ranges;
193
194        display-controller@1a01000 {
195            compatible = "qcom,msm8916-mdp5", "qcom,mdp5";
196            reg = <0x01a01000 0x89000>;
197            reg-names = "mdp_phys";
198
199            interrupt-parent = <&mdss>;
200            interrupts = <0>;
201
202            clocks = <&gcc GCC_MDSS_AHB_CLK>,
203                     <&gcc GCC_MDSS_AXI_CLK>,
204                     <&gcc GCC_MDSS_MDP_CLK>,
205                     <&gcc GCC_MDSS_VSYNC_CLK>;
206            clock-names = "iface",
207                      "bus",
208                      "core",
209                      "vsync";
210
211            iommus = <&apps_iommu 4>;
212
213            ports {
214                #address-cells = <1>;
215                #size-cells = <0>;
216
217                port@0 {
218                    reg = <0>;
219                    mdp5_intf1_out: endpoint {
220                        remote-endpoint = <&dsi0_in>;
221                    };
222                };
223            };
224        };
225    };
226...
227