xref: /linux/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml (revision d6296cb65320be16dbf20f2fd584ddc25f3437cd) 
1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Mobile Display SubSystem (MDSS)
8
9maintainers:
10  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11  - Rob Clark <robdclark@gmail.com>
12
13description:
14  This is the bindings documentation for the Mobile Display Subsytem(MDSS) that
15  encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc.
16
17properties:
18  $nodename:
19    pattern: "^display-subsystem@[0-9a-f]+$"
20
21  compatible:
22    enum:
23      - qcom,mdss
24
25  reg:
26    minItems: 2
27    maxItems: 3
28
29  reg-names:
30    minItems: 2
31    items:
32      - const: mdss_phys
33      - const: vbif_phys
34      - const: vbif_nrt_phys
35
36  interrupts:
37    maxItems: 1
38
39  interrupt-controller: true
40
41  "#interrupt-cells":
42    const: 1
43
44  power-domains:
45    maxItems: 1
46    description: |
47      The MDSS power domain provided by GCC
48
49  clocks:
50    oneOf:
51      - minItems: 3
52        items:
53          - description: Display abh clock
54          - description: Display axi clock
55          - description: Display vsync clock
56          - description: Display core clock
57      - minItems: 1
58        items:
59          - description: Display abh clock
60          - description: Display core clock
61
62  clock-names:
63    oneOf:
64      - minItems: 3
65        items:
66          - const: iface
67          - const: bus
68          - const: vsync
69          - const: core
70      - minItems: 1
71        items:
72          - const: iface
73          - const: core
74
75  "#address-cells":
76    const: 1
77
78  "#size-cells":
79    const: 1
80
81  ranges: true
82
83  resets:
84    items:
85      - description: MDSS_CORE reset
86
87required:
88  - compatible
89  - reg
90  - reg-names
91  - interrupts
92  - interrupt-controller
93  - "#interrupt-cells"
94  - power-domains
95  - clocks
96  - clock-names
97  - "#address-cells"
98  - "#size-cells"
99  - ranges
100
101patternProperties:
102  "^display-controller@[1-9a-f][0-9a-f]*$":
103    type: object
104    properties:
105      compatible:
106        contains:
107          const: qcom,mdp5
108
109  "^dsi@[1-9a-f][0-9a-f]*$":
110    type: object
111    properties:
112      compatible:
113        contains:
114          const: qcom,mdss-dsi-ctrl
115
116  "^phy@[1-9a-f][0-9a-f]*$":
117    type: object
118    properties:
119      compatible:
120        enum:
121          - qcom,dsi-phy-14nm
122          - qcom,dsi-phy-14nm-660
123          - qcom,dsi-phy-14nm-8953
124          - qcom,dsi-phy-20nm
125          - qcom,dsi-phy-28nm-hpm
126          - qcom,dsi-phy-28nm-lp
127          - qcom,hdmi-phy-8084
128          - qcom,hdmi-phy-8660
129          - qcom,hdmi-phy-8960
130          - qcom,hdmi-phy-8974
131          - qcom,hdmi-phy-8996
132
133  "^hdmi-tx@[1-9a-f][0-9a-f]*$":
134    type: object
135    properties:
136      compatible:
137        enum:
138          - qcom,hdmi-tx-8084
139          - qcom,hdmi-tx-8660
140          - qcom,hdmi-tx-8960
141          - qcom,hdmi-tx-8974
142          - qcom,hdmi-tx-8994
143          - qcom,hdmi-tx-8996
144
145additionalProperties: false
146
147examples:
148  - |
149    #include <dt-bindings/clock/qcom,gcc-msm8916.h>
150    #include <dt-bindings/interrupt-controller/arm-gic.h>
151    display-subsystem@1a00000 {
152        compatible = "qcom,mdss";
153        reg = <0x1a00000 0x1000>,
154              <0x1ac8000 0x3000>;
155        reg-names = "mdss_phys", "vbif_phys";
156
157        power-domains = <&gcc MDSS_GDSC>;
158
159        clocks = <&gcc GCC_MDSS_AHB_CLK>,
160                 <&gcc GCC_MDSS_AXI_CLK>,
161                 <&gcc GCC_MDSS_VSYNC_CLK>;
162        clock-names = "iface",
163                      "bus",
164                      "vsync";
165
166        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
167
168        interrupt-controller;
169        #interrupt-cells = <1>;
170
171        #address-cells = <1>;
172        #size-cells = <1>;
173        ranges;
174
175        display-controller@1a01000 {
176            compatible = "qcom,msm8916-mdp5", "qcom,mdp5";
177            reg = <0x01a01000 0x89000>;
178            reg-names = "mdp_phys";
179
180            interrupt-parent = <&mdss>;
181            interrupts = <0>;
182
183            clocks = <&gcc GCC_MDSS_AHB_CLK>,
184                     <&gcc GCC_MDSS_AXI_CLK>,
185                     <&gcc GCC_MDSS_MDP_CLK>,
186                     <&gcc GCC_MDSS_VSYNC_CLK>;
187            clock-names = "iface",
188                      "bus",
189                      "core",
190                      "vsync";
191
192            iommus = <&apps_iommu 4>;
193
194            ports {
195                #address-cells = <1>;
196                #size-cells = <0>;
197
198                port@0 {
199                    reg = <0>;
200                    mdp5_intf1_out: endpoint {
201                        remote-endpoint = <&dsi0_in>;
202                    };
203                };
204            };
205        };
206    };
207...
208