xref: /linux/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml (revision 55d0969c451159cff86949b38c39171cab962069) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,mdp5.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Adreno/Snapdragon Mobile Display controller (MDP5)
8
9description:
10  MDP5 display controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994
11  and MSM8996.
12
13maintainers:
14  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
15  - Rob Clark <robdclark@gmail.com>
16
17properties:
18  compatible:
19    oneOf:
20      - const: qcom,mdp5
21        deprecated: true
22      - items:
23          - enum:
24              - qcom,apq8084-mdp5
25              - qcom,msm8226-mdp5
26              - qcom,msm8916-mdp5
27              - qcom,msm8917-mdp5
28              - qcom,msm8937-mdp5
29              - qcom,msm8953-mdp5
30              - qcom,msm8974-mdp5
31              - qcom,msm8976-mdp5
32              - qcom,msm8994-mdp5
33              - qcom,msm8996-mdp5
34              - qcom,sdm630-mdp5
35              - qcom,sdm660-mdp5
36          - const: qcom,mdp5
37
38  $nodename:
39    pattern: '^display-controller@[0-9a-f]+$'
40
41  reg:
42    maxItems: 1
43
44  reg-names:
45    items:
46      - const: mdp_phys
47
48  interrupts:
49    maxItems: 1
50
51  clocks:
52    minItems: 4
53    maxItems: 7
54
55  clock-names:
56    oneOf:
57      - minItems: 4
58        items:
59          - const: iface
60          - const: bus
61          - const: core
62          - const: vsync
63          - const: lut
64          - const: tbu
65          - const: tbu_rt
66        # MSM8996 has additional iommu clock
67      - items:
68          - const: iface
69          - const: bus
70          - const: core
71          - const: iommu
72          - const: vsync
73
74  interconnects:
75    minItems: 1
76    items:
77      - description: Interconnect path from mdp0 (or a single mdp) port to the data bus
78      - description: Interconnect path from mdp1 port to the data bus
79      - description: Interconnect path from rotator port to the data bus
80
81  interconnect-names:
82    minItems: 1
83    items:
84      - const: mdp0-mem
85      - const: mdp1-mem
86      - const: rotator-mem
87
88  iommus:
89    items:
90      - description: apps SMMU with the Stream-ID mask for Hard-Fail port0
91
92  power-domains:
93    maxItems: 1
94
95  operating-points-v2: true
96  opp-table:
97    type: object
98
99  ports:
100    $ref: /schemas/graph.yaml#/properties/ports
101    description: >
102      Contains the list of output ports from DPU device. These ports
103      connect to interfaces that are external to the DPU hardware,
104      such as DSI, DP etc. MDP5 devices support up to 4 ports:
105      one or two DSI ports, HDMI and eDP.
106
107    patternProperties:
108      "^port@[0-3]+$":
109        $ref: /schemas/graph.yaml#/properties/port
110
111    # at least one port is required
112    required:
113      - port@0
114
115required:
116  - compatible
117  - reg
118  - reg-names
119  - clocks
120  - clock-names
121  - ports
122
123additionalProperties: false
124
125examples:
126  - |
127    #include <dt-bindings/clock/qcom,gcc-msm8916.h>
128    #include <dt-bindings/interrupt-controller/arm-gic.h>
129    display-controller@1a01000 {
130        compatible = "qcom,mdp5";
131        reg = <0x1a01000 0x90000>;
132        reg-names = "mdp_phys";
133
134        interrupt-parent = <&mdss>;
135        interrupts = <0>;
136
137        clocks = <&gcc GCC_MDSS_AHB_CLK>,
138                 <&gcc GCC_MDSS_AXI_CLK>,
139                 <&gcc GCC_MDSS_MDP_CLK>,
140                 <&gcc GCC_MDSS_VSYNC_CLK>;
141        clock-names = "iface",
142                      "bus",
143                      "core",
144                      "vsync";
145
146        ports {
147            #address-cells = <1>;
148            #size-cells = <0>;
149
150            port@0 {
151                reg = <0>;
152                endpoint {
153                    remote-endpoint = <&dsi0_in>;
154                };
155            };
156        };
157    };
158...
159