1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/msm/qcom,glymur-mdss.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Glymur Display MDSS 8 9maintainers: 10 - Abel Vesa <abel.vesa@linaro.org> 11 12description: 13 Glymur MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like 14 DPU display controller, DP interfaces, etc. 15 16$ref: /schemas/display/msm/mdss-common.yaml# 17 18properties: 19 compatible: 20 const: qcom,glymur-mdss 21 22 clocks: 23 items: 24 - description: Display AHB 25 - description: Display hf AXI 26 - description: Display core 27 28 iommus: 29 maxItems: 1 30 31 interconnects: 32 items: 33 - description: Interconnect path from mdp0 port to the data bus 34 - description: Interconnect path from CPU to the reg bus 35 36 interconnect-names: 37 items: 38 - const: mdp0-mem 39 - const: cpu-cfg 40 41patternProperties: 42 "^display-controller@[0-9a-f]+$": 43 type: object 44 additionalProperties: true 45 properties: 46 compatible: 47 const: qcom,glymur-dpu 48 49 "^displayport-controller@[0-9a-f]+$": 50 type: object 51 additionalProperties: true 52 properties: 53 compatible: 54 const: qcom,glymur-dp 55 56 "^phy@[0-9a-f]+$": 57 type: object 58 additionalProperties: true 59 properties: 60 compatible: 61 const: qcom,glymur-dp-phy 62 63required: 64 - compatible 65 66unevaluatedProperties: false 67 68examples: 69 - | 70 #include <dt-bindings/clock/qcom,rpmh.h> 71 #include <dt-bindings/interconnect/qcom,icc.h> 72 #include <dt-bindings/interconnect/qcom,glymur-rpmh.h> 73 #include <dt-bindings/interrupt-controller/arm-gic.h> 74 #include <dt-bindings/phy/phy-qcom-qmp.h> 75 #include <dt-bindings/power/qcom,rpmhpd.h> 76 77 display-subsystem@ae00000 { 78 compatible = "qcom,glymur-mdss"; 79 reg = <0x0ae00000 0x1000>; 80 reg-names = "mdss"; 81 82 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 83 84 clocks = <&dispcc_ahb_clk>, 85 <&gcc_disp_hf_axi_clk>, 86 <&dispcc_mdp_clk>; 87 clock-names = "bus", "nrt_bus", "core"; 88 89 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 90 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 91 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 92 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 93 interconnect-names = "mdp0-mem", 94 "cpu-cfg"; 95 96 resets = <&disp_cc_mdss_core_bcr>; 97 98 power-domains = <&mdss_gdsc>; 99 100 iommus = <&apps_smmu 0x1c00 0x2>; 101 102 interrupt-controller; 103 #interrupt-cells = <1>; 104 105 #address-cells = <1>; 106 #size-cells = <1>; 107 ranges; 108 109 display-controller@ae01000 { 110 compatible = "qcom,glymur-dpu"; 111 reg = <0x0ae01000 0x8f000>, 112 <0x0aeb0000 0x2008>; 113 reg-names = "mdp", "vbif"; 114 115 clocks = <&gcc_axi_clk>, 116 <&dispcc_ahb_clk>, 117 <&dispcc_mdp_lut_clk>, 118 <&dispcc_mdp_clk>, 119 <&dispcc_mdp_vsync_clk>; 120 clock-names = "nrt_bus", 121 "iface", 122 "lut", 123 "core", 124 "vsync"; 125 126 assigned-clocks = <&dispcc_mdp_vsync_clk>; 127 assigned-clock-rates = <19200000>; 128 129 operating-points-v2 = <&mdp_opp_table>; 130 power-domains = <&rpmhpd RPMHPD_MMCX>; 131 132 interrupt-parent = <&mdss>; 133 interrupts = <0>; 134 135 ports { 136 #address-cells = <1>; 137 #size-cells = <0>; 138 139 port@0 { 140 reg = <0>; 141 dpu_intf1_out: endpoint { 142 remote-endpoint = <&dsi0_in>; 143 }; 144 }; 145 146 port@1 { 147 reg = <1>; 148 dpu_intf2_out: endpoint { 149 remote-endpoint = <&dsi1_in>; 150 }; 151 }; 152 }; 153 154 mdp_opp_table: opp-table { 155 compatible = "operating-points-v2"; 156 157 opp-200000000 { 158 opp-hz = /bits/ 64 <200000000>; 159 required-opps = <&rpmhpd_opp_low_svs>; 160 }; 161 162 opp-325000000 { 163 opp-hz = /bits/ 64 <325000000>; 164 required-opps = <&rpmhpd_opp_svs>; 165 }; 166 167 opp-375000000 { 168 opp-hz = /bits/ 64 <375000000>; 169 required-opps = <&rpmhpd_opp_svs_l1>; 170 }; 171 172 opp-514000000 { 173 opp-hz = /bits/ 64 <514000000>; 174 required-opps = <&rpmhpd_opp_nom>; 175 }; 176 }; 177 }; 178 179 displayport-controller@af54000 { 180 compatible = "qcom,glymur-dp"; 181 reg = <0xaf54000 0x200>, 182 <0xaf54200 0x200>, 183 <0xaf55000 0xc00>, 184 <0xaf56000 0x400>, 185 <0xaf57000 0x400>, 186 <0xaf58000 0x400>, 187 <0xaf59000 0x400>, 188 <0xaf5a000 0x600>, 189 <0xaf5b000 0x600>; 190 191 interrupt-parent = <&mdss>; 192 interrupts = <12>; 193 194 clocks = <&dispcc_mdss_ahb_clk>, 195 <&dispcc_dptx0_aux_clk>, 196 <&dispcc_dptx0_link_clk>, 197 <&dispcc_dptx0_link_intf_clk>, 198 <&dispcc_dptx0_pixel0_clk>, 199 <&dispcc_dptx0_pixel1_clk>; 200 clock-names = "core_iface", 201 "core_aux", 202 "ctrl_link", 203 "ctrl_link_iface", 204 "stream_pixel", 205 "stream_1_pixel"; 206 207 assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>, 208 <&dispcc_mdss_dptx0_pixel0_clk_src>, 209 <&dispcc_mdss_dptx0_pixel1_clk_src>; 210 assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 211 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 212 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 213 214 operating-points-v2 = <&mdss_dp0_opp_table>; 215 216 power-domains = <&rpmhpd RPMHPD_MMCX>; 217 218 phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>; 219 phy-names = "dp"; 220 221 #sound-dai-cells = <0>; 222 223 ports { 224 #address-cells = <1>; 225 #size-cells = <0>; 226 227 port@0 { 228 reg = <0>; 229 230 mdss_dp0_in: endpoint { 231 remote-endpoint = <&mdss_intf0_out>; 232 }; 233 }; 234 235 port@1 { 236 reg = <1>; 237 238 mdss_dp0_out: endpoint { 239 }; 240 }; 241 }; 242 243 mdss_dp0_opp_table: opp-table { 244 compatible = "operating-points-v2"; 245 246 opp-160000000 { 247 opp-hz = /bits/ 64 <160000000>; 248 required-opps = <&rpmhpd_opp_low_svs>; 249 }; 250 251 opp-270000000 { 252 opp-hz = /bits/ 64 <270000000>; 253 required-opps = <&rpmhpd_opp_svs>; 254 }; 255 256 opp-540000000 { 257 opp-hz = /bits/ 64 <540000000>; 258 required-opps = <&rpmhpd_opp_svs_l1>; 259 }; 260 261 opp-810000000 { 262 opp-hz = /bits/ 64 <810000000>; 263 required-opps = <&rpmhpd_opp_nom>; 264 }; 265 }; 266 }; 267 }; 268... 269