xref: /linux/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml (revision e96150a6dc146779fc67a9a016339d861b5ec05a) 
1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QCM220 Display MDSS
8
9maintainers:
10  - Loic Poulain <loic.poulain@linaro.org>
11
12description:
13  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14  sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
15  are mentioned for QCM2290 target.
16
17$ref: /schemas/display/msm/mdss-common.yaml#
18
19properties:
20  compatible:
21    items:
22      - const: qcom,qcm2290-mdss
23
24  clocks:
25    items:
26      - description: Display AHB clock from gcc
27      - description: Display AXI clock
28      - description: Display core clock
29
30  clock-names:
31    items:
32      - const: iface
33      - const: bus
34      - const: core
35
36  iommus:
37    maxItems: 2
38
39  interconnects:
40    maxItems: 1
41
42  interconnect-names:
43    maxItems: 1
44
45patternProperties:
46  "^display-controller@[0-9a-f]+$":
47    type: object
48    properties:
49      compatible:
50        const: qcom,qcm2290-dpu
51
52  "^dsi@[0-9a-f]+$":
53    type: object
54    properties:
55      compatible:
56        const: qcom,dsi-ctrl-6g-qcm2290
57
58  "^phy@[0-9a-f]+$":
59    type: object
60    properties:
61      compatible:
62        const: qcom,dsi-phy-14nm-2290
63
64required:
65  - compatible
66
67unevaluatedProperties: false
68
69examples:
70  - |
71    #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
72    #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
73    #include <dt-bindings/clock/qcom,rpmcc.h>
74    #include <dt-bindings/interrupt-controller/arm-gic.h>
75    #include <dt-bindings/interconnect/qcom,qcm2290.h>
76    #include <dt-bindings/power/qcom-rpmpd.h>
77
78    display-subsystem@5e00000 {
79        #address-cells = <1>;
80        #size-cells = <1>;
81        compatible = "qcom,qcm2290-mdss";
82        reg = <0x05e00000 0x1000>;
83        reg-names = "mdss";
84        power-domains = <&dispcc MDSS_GDSC>;
85        clocks = <&gcc GCC_DISP_AHB_CLK>,
86                 <&gcc GCC_DISP_HF_AXI_CLK>,
87                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
88        clock-names = "iface", "bus", "core";
89
90        interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
91        interrupt-controller;
92        #interrupt-cells = <1>;
93
94        interconnects = <&mmrt_virt MASTER_MDP0 &bimc SLAVE_EBI1>;
95        interconnect-names = "mdp0-mem";
96
97        iommus = <&apps_smmu 0x420 0x2>,
98                 <&apps_smmu 0x421 0x0>;
99        ranges;
100
101        display-controller@5e01000 {
102            compatible = "qcom,qcm2290-dpu";
103            reg = <0x05e01000 0x8f000>,
104                  <0x05eb0000 0x2008>;
105            reg-names = "mdp", "vbif";
106
107            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
108                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
109                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
110                     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
111                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
112            clock-names = "bus", "iface", "core", "lut", "vsync";
113
114            operating-points-v2 = <&mdp_opp_table>;
115            power-domains = <&rpmpd QCM2290_VDDCX>;
116
117            interrupt-parent = <&mdss>;
118            interrupts = <0>;
119
120            ports {
121                #address-cells = <1>;
122                #size-cells = <0>;
123
124                port@0 {
125                    reg = <0>;
126                    dpu_intf1_out: endpoint {
127                        remote-endpoint = <&dsi0_in>;
128                    };
129                };
130            };
131        };
132
133        dsi@5e94000 {
134            compatible = "qcom,dsi-ctrl-6g-qcm2290";
135            reg = <0x05e94000 0x400>;
136            reg-names = "dsi_ctrl";
137
138            interrupt-parent = <&mdss>;
139            interrupts = <4>;
140
141            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
142                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
143                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
144                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
145                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
146                     <&gcc GCC_DISP_HF_AXI_CLK>;
147            clock-names = "byte",
148                          "byte_intf",
149                          "pixel",
150                          "core",
151                          "iface",
152                          "bus";
153            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
154            assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
155
156            operating-points-v2 = <&dsi_opp_table>;
157            power-domains = <&rpmpd QCM2290_VDDCX>;
158
159            phys = <&dsi0_phy>;
160            phy-names = "dsi";
161
162            #address-cells = <1>;
163            #size-cells = <0>;
164
165            ports {
166                #address-cells = <1>;
167                #size-cells = <0>;
168
169                port@0 {
170                    reg = <0>;
171                    dsi0_in: endpoint {
172                        remote-endpoint = <&dpu_intf1_out>;
173                    };
174                };
175
176                port@1 {
177                    reg = <1>;
178                    dsi0_out: endpoint {
179                    };
180                };
181            };
182        };
183
184        dsi0_phy: phy@5e94400 {
185            compatible = "qcom,dsi-phy-14nm-2290";
186            reg = <0x05e94400 0x100>,
187                  <0x05e94500 0x300>,
188                  <0x05e94800 0x188>;
189            reg-names = "dsi_phy",
190                        "dsi_phy_lane",
191                        "dsi_pll";
192
193            #clock-cells = <1>;
194            #phy-cells = <0>;
195
196            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
197            clock-names = "iface", "ref";
198            vcca-supply = <&vreg_dsi_phy>;
199        };
200    };
201...
202