xref: /linux/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml (revision e5266ca38294c6eba48f5c9cd3d0402d619d7c05) 
1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QCM220 Display MDSS
8
9maintainers:
10  - Loic Poulain <loic.poulain@linaro.org>
11
12description:
13  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14  sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
15  are mentioned for QCM2290 target.
16
17$ref: /schemas/display/msm/mdss-common.yaml#
18
19properties:
20  compatible:
21    items:
22      - const: qcom,qcm2290-mdss
23
24  clocks:
25    items:
26      - description: Display AHB clock from gcc
27      - description: Display AXI clock
28      - description: Display core clock
29
30  clock-names:
31    items:
32      - const: iface
33      - const: bus
34      - const: core
35
36  iommus:
37    maxItems: 2
38
39  interconnects:
40    maxItems: 1
41
42  interconnect-names:
43    maxItems: 1
44
45patternProperties:
46  "^display-controller@[0-9a-f]+$":
47    type: object
48    properties:
49      compatible:
50        const: qcom,qcm2290-dpu
51
52  "^dsi@[0-9a-f]+$":
53    type: object
54    properties:
55      compatible:
56        const: qcom,dsi-ctrl-6g-qcm2290
57
58  "^phy@[0-9a-f]+$":
59    type: object
60    properties:
61      compatible:
62        const: qcom,dsi-phy-14nm-2290
63
64unevaluatedProperties: false
65
66examples:
67  - |
68    #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
69    #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
70    #include <dt-bindings/clock/qcom,rpmcc.h>
71    #include <dt-bindings/interrupt-controller/arm-gic.h>
72    #include <dt-bindings/interconnect/qcom,qcm2290.h>
73    #include <dt-bindings/power/qcom-rpmpd.h>
74
75    display-subsystem@5e00000 {
76        #address-cells = <1>;
77        #size-cells = <1>;
78        compatible = "qcom,qcm2290-mdss";
79        reg = <0x05e00000 0x1000>;
80        reg-names = "mdss";
81        power-domains = <&dispcc MDSS_GDSC>;
82        clocks = <&gcc GCC_DISP_AHB_CLK>,
83                 <&gcc GCC_DISP_HF_AXI_CLK>,
84                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
85        clock-names = "iface", "bus", "core";
86
87        interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
88        interrupt-controller;
89        #interrupt-cells = <1>;
90
91        interconnects = <&mmrt_virt MASTER_MDP0 &bimc SLAVE_EBI1>;
92        interconnect-names = "mdp0-mem";
93
94        iommus = <&apps_smmu 0x420 0x2>,
95                 <&apps_smmu 0x421 0x0>;
96        ranges;
97
98        display-controller@5e01000 {
99            compatible = "qcom,qcm2290-dpu";
100            reg = <0x05e01000 0x8f000>,
101                  <0x05eb0000 0x2008>;
102            reg-names = "mdp", "vbif";
103
104            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
105                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
106                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
107                     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
108                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
109            clock-names = "bus", "iface", "core", "lut", "vsync";
110
111            operating-points-v2 = <&mdp_opp_table>;
112            power-domains = <&rpmpd QCM2290_VDDCX>;
113
114            interrupt-parent = <&mdss>;
115            interrupts = <0>;
116
117            ports {
118                #address-cells = <1>;
119                #size-cells = <0>;
120
121                port@0 {
122                    reg = <0>;
123                    dpu_intf1_out: endpoint {
124                        remote-endpoint = <&dsi0_in>;
125                    };
126                };
127            };
128        };
129
130        dsi@5e94000 {
131            compatible = "qcom,dsi-ctrl-6g-qcm2290";
132            reg = <0x05e94000 0x400>;
133            reg-names = "dsi_ctrl";
134
135            interrupt-parent = <&mdss>;
136            interrupts = <4>;
137
138            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
139                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
140                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
141                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
142                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
143                     <&gcc GCC_DISP_HF_AXI_CLK>;
144            clock-names = "byte",
145                          "byte_intf",
146                          "pixel",
147                          "core",
148                          "iface",
149                          "bus";
150            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
151            assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
152
153            operating-points-v2 = <&dsi_opp_table>;
154            power-domains = <&rpmpd QCM2290_VDDCX>;
155
156            phys = <&dsi0_phy>;
157            phy-names = "dsi";
158
159            #address-cells = <1>;
160            #size-cells = <0>;
161
162            ports {
163                #address-cells = <1>;
164                #size-cells = <0>;
165
166                port@0 {
167                    reg = <0>;
168                    dsi0_in: endpoint {
169                        remote-endpoint = <&dpu_intf1_out>;
170                    };
171                };
172
173                port@1 {
174                    reg = <1>;
175                    dsi0_out: endpoint {
176                    };
177                };
178            };
179        };
180
181        dsi0_phy: phy@5e94400 {
182            compatible = "qcom,dsi-phy-14nm-2290";
183            reg = <0x05e94400 0x100>,
184                  <0x05e94500 0x300>,
185                  <0x05e94800 0x188>;
186            reg-names = "dsi_phy",
187                        "dsi_phy_lane",
188                        "dsi_pll";
189
190            #clock-cells = <1>;
191            #phy-cells = <0>;
192
193            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
194            clock-names = "iface", "ref";
195            vcca-supply = <&vreg_dsi_phy>;
196        };
197    };
198...
199