1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-mdss.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm QCM220 Display MDSS 8 9maintainers: 10 - Loic Poulain <loic.poulain@linaro.org> 11 12description: 13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates 14 sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS 15 are mentioned for QCM2290 target. 16 17$ref: /schemas/display/msm/mdss-common.yaml# 18 19properties: 20 compatible: 21 const: qcom,qcm2290-mdss 22 23 clocks: 24 items: 25 - description: Display AHB clock from gcc 26 - description: Display AXI clock 27 - description: Display core clock 28 29 clock-names: 30 items: 31 - const: iface 32 - const: bus 33 - const: core 34 35 iommus: 36 maxItems: 2 37 38 interconnects: 39 maxItems: 1 40 41 interconnect-names: 42 maxItems: 1 43 44patternProperties: 45 "^display-controller@[0-9a-f]+$": 46 type: object 47 additionalProperties: true 48 49 properties: 50 compatible: 51 const: qcom,qcm2290-dpu 52 53 "^dsi@[0-9a-f]+$": 54 type: object 55 additionalProperties: true 56 57 properties: 58 compatible: 59 const: qcom,dsi-ctrl-6g-qcm2290 60 61 "^phy@[0-9a-f]+$": 62 type: object 63 additionalProperties: true 64 65 properties: 66 compatible: 67 const: qcom,dsi-phy-14nm-2290 68 69required: 70 - compatible 71 72unevaluatedProperties: false 73 74examples: 75 - | 76 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h> 77 #include <dt-bindings/clock/qcom,gcc-qcm2290.h> 78 #include <dt-bindings/clock/qcom,rpmcc.h> 79 #include <dt-bindings/interrupt-controller/arm-gic.h> 80 #include <dt-bindings/interconnect/qcom,qcm2290.h> 81 #include <dt-bindings/power/qcom-rpmpd.h> 82 83 display-subsystem@5e00000 { 84 #address-cells = <1>; 85 #size-cells = <1>; 86 compatible = "qcom,qcm2290-mdss"; 87 reg = <0x05e00000 0x1000>; 88 reg-names = "mdss"; 89 power-domains = <&dispcc MDSS_GDSC>; 90 clocks = <&gcc GCC_DISP_AHB_CLK>, 91 <&gcc GCC_DISP_HF_AXI_CLK>, 92 <&dispcc DISP_CC_MDSS_MDP_CLK>; 93 clock-names = "iface", "bus", "core"; 94 95 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 96 interrupt-controller; 97 #interrupt-cells = <1>; 98 99 interconnects = <&mmrt_virt MASTER_MDP0 &bimc SLAVE_EBI1>; 100 interconnect-names = "mdp0-mem"; 101 102 iommus = <&apps_smmu 0x420 0x2>, 103 <&apps_smmu 0x421 0x0>; 104 ranges; 105 106 display-controller@5e01000 { 107 compatible = "qcom,qcm2290-dpu"; 108 reg = <0x05e01000 0x8f000>, 109 <0x05eb0000 0x2008>; 110 reg-names = "mdp", "vbif"; 111 112 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 113 <&dispcc DISP_CC_MDSS_AHB_CLK>, 114 <&dispcc DISP_CC_MDSS_MDP_CLK>, 115 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 116 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 117 clock-names = "bus", "iface", "core", "lut", "vsync"; 118 119 operating-points-v2 = <&mdp_opp_table>; 120 power-domains = <&rpmpd QCM2290_VDDCX>; 121 122 interrupt-parent = <&mdss>; 123 interrupts = <0>; 124 125 ports { 126 #address-cells = <1>; 127 #size-cells = <0>; 128 129 port@0 { 130 reg = <0>; 131 dpu_intf1_out: endpoint { 132 remote-endpoint = <&dsi0_in>; 133 }; 134 }; 135 }; 136 }; 137 138 dsi@5e94000 { 139 compatible = "qcom,dsi-ctrl-6g-qcm2290"; 140 reg = <0x05e94000 0x400>; 141 reg-names = "dsi_ctrl"; 142 143 interrupt-parent = <&mdss>; 144 interrupts = <4>; 145 146 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 147 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 148 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 149 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 150 <&dispcc DISP_CC_MDSS_AHB_CLK>, 151 <&gcc GCC_DISP_HF_AXI_CLK>; 152 clock-names = "byte", 153 "byte_intf", 154 "pixel", 155 "core", 156 "iface", 157 "bus"; 158 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 159 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 160 161 operating-points-v2 = <&dsi_opp_table>; 162 power-domains = <&rpmpd QCM2290_VDDCX>; 163 164 phys = <&dsi0_phy>; 165 phy-names = "dsi"; 166 167 #address-cells = <1>; 168 #size-cells = <0>; 169 170 ports { 171 #address-cells = <1>; 172 #size-cells = <0>; 173 174 port@0 { 175 reg = <0>; 176 dsi0_in: endpoint { 177 remote-endpoint = <&dpu_intf1_out>; 178 }; 179 }; 180 181 port@1 { 182 reg = <1>; 183 dsi0_out: endpoint { 184 }; 185 }; 186 }; 187 }; 188 189 dsi0_phy: phy@5e94400 { 190 compatible = "qcom,dsi-phy-14nm-2290"; 191 reg = <0x05e94400 0x100>, 192 <0x05e94500 0x300>, 193 <0x05e94800 0x188>; 194 reg-names = "dsi_phy", 195 "dsi_phy_lane", 196 "dsi_pll"; 197 198 #clock-cells = <1>; 199 #phy-cells = <0>; 200 201 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 202 clock-names = "iface", "ref"; 203 vcca-supply = <&vreg_dsi_phy>; 204 }; 205 }; 206... 207