1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-mdss.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm QCM220 Display MDSS 8 9maintainers: 10 - Loic Poulain <loic.poulain@linaro.org> 11 12description: 13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates 14 sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS 15 are mentioned for QCM2290 target. 16 17$ref: /schemas/display/msm/mdss-common.yaml# 18 19properties: 20 compatible: 21 const: qcom,qcm2290-mdss 22 23 clocks: 24 items: 25 - description: Display AHB clock from gcc 26 - description: Display AXI clock 27 - description: Display core clock 28 29 clock-names: 30 items: 31 - const: iface 32 - const: bus 33 - const: core 34 35 iommus: 36 maxItems: 2 37 38 interconnects: 39 maxItems: 1 40 41 interconnect-names: 42 maxItems: 1 43 44patternProperties: 45 "^display-controller@[0-9a-f]+$": 46 type: object 47 properties: 48 compatible: 49 const: qcom,qcm2290-dpu 50 51 "^dsi@[0-9a-f]+$": 52 type: object 53 properties: 54 compatible: 55 const: qcom,dsi-ctrl-6g-qcm2290 56 57 "^phy@[0-9a-f]+$": 58 type: object 59 properties: 60 compatible: 61 const: qcom,dsi-phy-14nm-2290 62 63required: 64 - compatible 65 66unevaluatedProperties: false 67 68examples: 69 - | 70 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h> 71 #include <dt-bindings/clock/qcom,gcc-qcm2290.h> 72 #include <dt-bindings/clock/qcom,rpmcc.h> 73 #include <dt-bindings/interrupt-controller/arm-gic.h> 74 #include <dt-bindings/interconnect/qcom,qcm2290.h> 75 #include <dt-bindings/power/qcom-rpmpd.h> 76 77 display-subsystem@5e00000 { 78 #address-cells = <1>; 79 #size-cells = <1>; 80 compatible = "qcom,qcm2290-mdss"; 81 reg = <0x05e00000 0x1000>; 82 reg-names = "mdss"; 83 power-domains = <&dispcc MDSS_GDSC>; 84 clocks = <&gcc GCC_DISP_AHB_CLK>, 85 <&gcc GCC_DISP_HF_AXI_CLK>, 86 <&dispcc DISP_CC_MDSS_MDP_CLK>; 87 clock-names = "iface", "bus", "core"; 88 89 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 90 interrupt-controller; 91 #interrupt-cells = <1>; 92 93 interconnects = <&mmrt_virt MASTER_MDP0 &bimc SLAVE_EBI1>; 94 interconnect-names = "mdp0-mem"; 95 96 iommus = <&apps_smmu 0x420 0x2>, 97 <&apps_smmu 0x421 0x0>; 98 ranges; 99 100 display-controller@5e01000 { 101 compatible = "qcom,qcm2290-dpu"; 102 reg = <0x05e01000 0x8f000>, 103 <0x05eb0000 0x2008>; 104 reg-names = "mdp", "vbif"; 105 106 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 107 <&dispcc DISP_CC_MDSS_AHB_CLK>, 108 <&dispcc DISP_CC_MDSS_MDP_CLK>, 109 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 110 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 111 clock-names = "bus", "iface", "core", "lut", "vsync"; 112 113 operating-points-v2 = <&mdp_opp_table>; 114 power-domains = <&rpmpd QCM2290_VDDCX>; 115 116 interrupt-parent = <&mdss>; 117 interrupts = <0>; 118 119 ports { 120 #address-cells = <1>; 121 #size-cells = <0>; 122 123 port@0 { 124 reg = <0>; 125 dpu_intf1_out: endpoint { 126 remote-endpoint = <&dsi0_in>; 127 }; 128 }; 129 }; 130 }; 131 132 dsi@5e94000 { 133 compatible = "qcom,dsi-ctrl-6g-qcm2290"; 134 reg = <0x05e94000 0x400>; 135 reg-names = "dsi_ctrl"; 136 137 interrupt-parent = <&mdss>; 138 interrupts = <4>; 139 140 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 141 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 142 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 143 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 144 <&dispcc DISP_CC_MDSS_AHB_CLK>, 145 <&gcc GCC_DISP_HF_AXI_CLK>; 146 clock-names = "byte", 147 "byte_intf", 148 "pixel", 149 "core", 150 "iface", 151 "bus"; 152 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 153 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 154 155 operating-points-v2 = <&dsi_opp_table>; 156 power-domains = <&rpmpd QCM2290_VDDCX>; 157 158 phys = <&dsi0_phy>; 159 phy-names = "dsi"; 160 161 #address-cells = <1>; 162 #size-cells = <0>; 163 164 ports { 165 #address-cells = <1>; 166 #size-cells = <0>; 167 168 port@0 { 169 reg = <0>; 170 dsi0_in: endpoint { 171 remote-endpoint = <&dpu_intf1_out>; 172 }; 173 }; 174 175 port@1 { 176 reg = <1>; 177 dsi0_out: endpoint { 178 }; 179 }; 180 }; 181 }; 182 183 dsi0_phy: phy@5e94400 { 184 compatible = "qcom,dsi-phy-14nm-2290"; 185 reg = <0x05e94400 0x100>, 186 <0x05e94500 0x300>, 187 <0x05e94800 0x188>; 188 reg-names = "dsi_phy", 189 "dsi_phy_lane", 190 "dsi_pll"; 191 192 #clock-cells = <1>; 193 #phy-cells = <0>; 194 195 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 196 clock-names = "iface", "ref"; 197 vcca-supply = <&vreg_dsi_phy>; 198 }; 199 }; 200... 201