xref: /linux/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml (revision 25daacc60394d1c82b14b13ebfb87544e14a5f36) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QCM220 Display MDSS
8
9maintainers:
10  - Loic Poulain <loic.poulain@linaro.org>
11
12description:
13  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14  sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
15  are mentioned for QCM2290 target.
16
17$ref: /schemas/display/msm/mdss-common.yaml#
18
19properties:
20  compatible:
21    const: qcom,qcm2290-mdss
22
23  clocks:
24    items:
25      - description: Display AHB clock from gcc
26      - description: Display AXI clock
27      - description: Display core clock
28
29  clock-names:
30    items:
31      - const: iface
32      - const: bus
33      - const: core
34
35  iommus:
36    maxItems: 2
37
38  interconnects:
39    maxItems: 1
40
41  interconnect-names:
42    maxItems: 1
43
44patternProperties:
45  "^display-controller@[0-9a-f]+$":
46    type: object
47    additionalProperties: true
48
49    properties:
50      compatible:
51        const: qcom,qcm2290-dpu
52
53  "^dsi@[0-9a-f]+$":
54    type: object
55    additionalProperties: true
56
57    properties:
58      compatible:
59        items:
60          - const: qcom,qcm2290-dsi-ctrl
61          - const: qcom,mdss-dsi-ctrl
62
63  "^phy@[0-9a-f]+$":
64    type: object
65    additionalProperties: true
66
67    properties:
68      compatible:
69        const: qcom,dsi-phy-14nm-2290
70
71required:
72  - compatible
73
74unevaluatedProperties: false
75
76examples:
77  - |
78    #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
79    #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
80    #include <dt-bindings/clock/qcom,rpmcc.h>
81    #include <dt-bindings/interrupt-controller/arm-gic.h>
82    #include <dt-bindings/interconnect/qcom,qcm2290.h>
83    #include <dt-bindings/power/qcom-rpmpd.h>
84
85    display-subsystem@5e00000 {
86        #address-cells = <1>;
87        #size-cells = <1>;
88        compatible = "qcom,qcm2290-mdss";
89        reg = <0x05e00000 0x1000>;
90        reg-names = "mdss";
91        power-domains = <&dispcc MDSS_GDSC>;
92        clocks = <&gcc GCC_DISP_AHB_CLK>,
93                 <&gcc GCC_DISP_HF_AXI_CLK>,
94                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
95        clock-names = "iface", "bus", "core";
96
97        interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
98        interrupt-controller;
99        #interrupt-cells = <1>;
100
101        interconnects = <&mmrt_virt MASTER_MDP0 &bimc SLAVE_EBI1>;
102        interconnect-names = "mdp0-mem";
103
104        iommus = <&apps_smmu 0x420 0x2>,
105                 <&apps_smmu 0x421 0x0>;
106        ranges;
107
108        display-controller@5e01000 {
109            compatible = "qcom,qcm2290-dpu";
110            reg = <0x05e01000 0x8f000>,
111                  <0x05eb0000 0x2008>;
112            reg-names = "mdp", "vbif";
113
114            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
115                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
116                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
117                     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
118                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
119            clock-names = "bus", "iface", "core", "lut", "vsync";
120
121            operating-points-v2 = <&mdp_opp_table>;
122            power-domains = <&rpmpd QCM2290_VDDCX>;
123
124            interrupt-parent = <&mdss>;
125            interrupts = <0>;
126
127            ports {
128                #address-cells = <1>;
129                #size-cells = <0>;
130
131                port@0 {
132                    reg = <0>;
133                    dpu_intf1_out: endpoint {
134                        remote-endpoint = <&dsi0_in>;
135                    };
136                };
137            };
138        };
139
140        dsi@5e94000 {
141            compatible = "qcom,qcm2290-dsi-ctrl",
142                         "qcom,mdss-dsi-ctrl";
143            reg = <0x05e94000 0x400>;
144            reg-names = "dsi_ctrl";
145
146            interrupt-parent = <&mdss>;
147            interrupts = <4>;
148
149            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
150                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
151                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
152                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
153                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
154                     <&gcc GCC_DISP_HF_AXI_CLK>;
155            clock-names = "byte",
156                          "byte_intf",
157                          "pixel",
158                          "core",
159                          "iface",
160                          "bus";
161            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
162            assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
163
164            operating-points-v2 = <&dsi_opp_table>;
165            power-domains = <&rpmpd QCM2290_VDDCX>;
166
167            phys = <&dsi0_phy>;
168            phy-names = "dsi";
169
170            #address-cells = <1>;
171            #size-cells = <0>;
172
173            ports {
174                #address-cells = <1>;
175                #size-cells = <0>;
176
177                port@0 {
178                    reg = <0>;
179                    dsi0_in: endpoint {
180                        remote-endpoint = <&dpu_intf1_out>;
181                    };
182                };
183
184                port@1 {
185                    reg = <1>;
186                    dsi0_out: endpoint {
187                    };
188                };
189            };
190        };
191
192        dsi0_phy: phy@5e94400 {
193            compatible = "qcom,dsi-phy-14nm-2290";
194            reg = <0x05e94400 0x100>,
195                  <0x05e94500 0x300>,
196                  <0x05e94800 0x188>;
197            reg-names = "dsi_phy",
198                        "dsi_phy_lane",
199                        "dsi_pll";
200
201            #clock-cells = <1>;
202            #phy-cells = <0>;
203
204            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
205            clock-names = "iface", "ref";
206            vcca-supply = <&vreg_dsi_phy>;
207        };
208    };
209...
210