1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/msm/mdss-common.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Display MDSS common properties 8 9maintainers: 10 - Krishna Manikandan <quic_mkrishn@quicinc.com> 11 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> 12 - Rob Clark <robdclark@gmail.com> 13 14description: 15 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates 16 sub-blocks like DPU display controller, DSI and DP interfaces etc. 17 18# Do not select this by default, otherwise it is also selected for qcom,mdss 19# devices. 20select: 21 false 22 23properties: 24 $nodename: 25 pattern: "^display-subsystem@[0-9a-f]+$" 26 27 reg: 28 maxItems: 1 29 30 reg-names: 31 const: mdss 32 33 power-domains: 34 maxItems: 1 35 36 clocks: 37 minItems: 2 38 maxItems: 4 39 40 clock-names: 41 minItems: 2 42 maxItems: 4 43 44 interrupts: 45 maxItems: 1 46 47 interrupt-controller: true 48 49 "#address-cells": true 50 51 "#size-cells": true 52 53 "#interrupt-cells": 54 const: 1 55 56 iommus: 57 minItems: 1 58 items: 59 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 60 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1 61 62 ranges: true 63 64 interconnects: 65 minItems: 1 66 items: 67 - description: Interconnect path from mdp0 (or a single mdp) port to the data bus 68 - description: Interconnect path from mdp1 port to the data bus 69 70 interconnect-names: 71 minItems: 1 72 items: 73 - const: mdp0-mem 74 - const: mdp1-mem 75 76 resets: 77 items: 78 - description: MDSS_CORE reset 79 80 memory-region: 81 maxItems: 1 82 description: 83 Phandle to a node describing a reserved framebuffer memory region. 84 For example, the splash memory region set up by the bootloader. 85 86required: 87 - reg 88 - reg-names 89 - power-domains 90 - clocks 91 - interrupts 92 - interrupt-controller 93 - iommus 94 - ranges 95 96additionalProperties: true 97