xref: /linux/Documentation/devicetree/bindings/display/msm/mdp4.yaml (revision df9c299371054cb725eef730fd0f1d0fe2ed6bb0) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/mdp4.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Adreno/Snapdragon MDP4 display controller
8
9description: >
10  MDP4 display controller found in SoCs like MSM8960, APQ8064 and MSM8660.
11
12maintainers:
13  - Rob Clark <robdclark@gmail.com>
14
15properties:
16  compatible:
17    const: qcom,mdp4
18
19  clocks:
20    minItems: 6
21    maxItems: 8
22
23  clock-names:
24    minItems: 6
25    items:
26      - const: core_clk
27      - const: iface_clk
28      - const: bus_clk
29      - const: lut_clk
30      - const: hdmi_clk
31      - const: tv_clk
32      - const: lcdc_clk
33      - const: pxo
34        description: XO used to drive the internal LVDS PLL
35
36  '#clock-cells':
37    const: 0
38
39  reg:
40    maxItems: 1
41
42  interrupts:
43    maxItems: 1
44
45  iommus:
46    maxItems: 4
47
48  ports:
49    $ref: /schemas/graph.yaml#/properties/ports
50    properties:
51      port@0:
52        $ref: /schemas/graph.yaml#/properties/port
53        description: LCDC/LVDS
54
55      port@1:
56        $ref: /schemas/graph.yaml#/properties/port
57        description: DSI1 Cmd / Video
58
59      port@2:
60        $ref: /schemas/graph.yaml#/properties/port
61        description: DSI2 Cmd / Video
62
63      port@3:
64        $ref: /schemas/graph.yaml#/properties/port
65        description: Digital TV
66
67  qcom,lcdc-align-lsb:
68    type: boolean
69    description: >
70      Indication that LSB alignment should be used for LCDC.
71      This is only valid for 18bpp panels.
72
73required:
74  - compatible
75  - reg
76  - clocks
77  - ports
78
79additionalProperties: false
80
81examples:
82  - |
83    mdp: mdp@5100000 {
84        compatible = "qcom,mdp4";
85        reg = <0x05100000 0xf0000>;
86        interrupts = <0 75 0>;
87        clock-names =
88            "core_clk",
89            "iface_clk",
90            "bus_clk",
91            "lut_clk",
92            "hdmi_clk",
93            "tv_clk";
94        clocks =
95            <&mmcc 77>,
96            <&mmcc 86>,
97            <&mmcc 102>,
98            <&mmcc 75>,
99            <&mmcc 97>,
100            <&mmcc 12>;
101
102        ports {
103            #address-cells = <1>;
104            #size-cells = <0>;
105
106            port@0 {
107                reg = <0>;
108                mdp_lvds_out: endpoint {
109                };
110            };
111
112            port@1 {
113                reg = <1>;
114                mdp_dsi1_out: endpoint {
115                };
116            };
117
118            port@2 {
119                reg = <2>;
120                mdp_dsi2_out: endpoint {
121                };
122            };
123
124            port@3 {
125                reg = <3>;
126                mdp_dtv_out: endpoint {
127                    remote-endpoint = <&hdmi_in>;
128                };
129            };
130        };
131    };
132