1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4 5$id: http://devicetree.org/schemas/display/msm/gpu.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: Adreno or Snapdragon GPUs 9 10maintainers: 11 - Rob Clark <robdclark@gmail.com> 12 13# dtschema does not select nodes based on pattern+const, so add custom select 14# as a work-around: 15select: 16 properties: 17 compatible: 18 contains: 19 enum: 20 - qcom,adreno 21 - amd,imageon 22 required: 23 - compatible 24 25properties: 26 compatible: 27 oneOf: 28 - description: | 29 The driver is parsing the compat string for Adreno to 30 figure out the chip-id. 31 items: 32 - pattern: '^qcom,adreno-[0-9a-f]{8}$' 33 - const: qcom,adreno 34 - description: | 35 The driver is parsing the compat string for Adreno to 36 figure out the gpu-id and patch level. 37 items: 38 - pattern: '^qcom,adreno-[3-7][0-9][0-9]\.[0-9]+$' 39 - const: qcom,adreno 40 - description: | 41 The driver is parsing the compat string for Imageon to 42 figure out the gpu-id and patch level. 43 items: 44 - pattern: '^amd,imageon-200\.[0-1]$' 45 - const: amd,imageon 46 47 clocks: 48 minItems: 1 49 maxItems: 7 50 51 clock-names: 52 minItems: 1 53 maxItems: 7 54 55 reg: 56 minItems: 1 57 maxItems: 3 58 59 reg-names: 60 minItems: 1 61 items: 62 - const: kgsl_3d0_reg_memory 63 - const: cx_mem 64 - const: cx_dbgc 65 66 interrupts: 67 maxItems: 1 68 69 interrupt-names: 70 maxItems: 1 71 72 interconnects: 73 minItems: 1 74 maxItems: 2 75 76 interconnect-names: 77 minItems: 1 78 items: 79 - const: gfx-mem 80 - const: ocmem 81 82 iommus: 83 minItems: 1 84 maxItems: 64 85 86 sram: 87 minItems: 1 88 maxItems: 4 89 description: 90 phandle to the On Chip Memory (OCMEM) that's present on some a3xx and 91 a4xx Snapdragon SoCs. See 92 Documentation/devicetree/bindings/sram/qcom,ocmem.yaml 93 94 operating-points-v2: true 95 opp-table: 96 type: object 97 98 power-domains: 99 maxItems: 1 100 101 zap-shader: 102 type: object 103 additionalProperties: false 104 description: | 105 For a5xx and a6xx devices this node contains a memory-region that 106 points to reserved memory to store the zap shader that can be used to 107 help bring the GPU out of secure mode. 108 properties: 109 memory-region: 110 maxItems: 1 111 112 firmware-name: 113 description: | 114 Default name of the firmware to load to the remote processor. 115 116 "#cooling-cells": 117 const: 2 118 119 nvmem-cell-names: 120 maxItems: 1 121 122 nvmem-cells: 123 description: efuse registers 124 maxItems: 1 125 126 qcom,gmu: 127 $ref: /schemas/types.yaml#/definitions/phandle 128 description: | 129 For GMU attached devices a phandle to the GMU device that will 130 control the power for the GPU. 131 132required: 133 - compatible 134 - reg 135 - interrupts 136 137additionalProperties: false 138 139allOf: 140 - if: 141 properties: 142 compatible: 143 contains: 144 oneOf: 145 - pattern: '^qcom,adreno-305\.[0-9]+$' 146 - pattern: '^qcom,adreno-330\.[0-9]+$' 147 then: 148 properties: 149 clocks: 150 minItems: 3 151 maxItems: 3 152 clock-names: 153 items: 154 - const: core 155 description: GPU Core clock 156 - const: iface 157 description: GPU Interface clock 158 - const: mem_iface 159 description: GPU Memory Interface clock 160 161 - if: 162 properties: 163 compatible: 164 contains: 165 pattern: '^qcom,adreno-306\.[0-9]+$' 166 then: 167 properties: 168 clocks: 169 minItems: 5 170 maxItems: 6 171 clock-names: 172 oneOf: 173 - items: 174 - const: core 175 description: GPU Core clock 176 - const: iface 177 description: GPU Interface clock 178 - const: mem_iface 179 description: GPU Memory Interface clock 180 - const: alt_mem_iface 181 description: GPU Alternative Memory Interface clock 182 - const: gfx3d 183 description: GPU 3D engine clock 184 - items: 185 - const: core 186 description: GPU Core clock 187 - const: iface 188 description: GPU Interface clock 189 - const: mem 190 description: GPU Memory clock 191 - const: mem_iface 192 description: GPU Memory Interface clock 193 - const: alt_mem_iface 194 description: GPU Alternative Memory Interface clock 195 - const: gfx3d 196 description: GPU 3D engine clock 197 198 - if: 199 properties: 200 compatible: 201 contains: 202 pattern: '^qcom,adreno-320\.[0-9]+$' 203 then: 204 properties: 205 clocks: 206 minItems: 4 207 maxItems: 4 208 clock-names: 209 items: 210 - const: core 211 description: GPU Core clock 212 - const: iface 213 description: GPU Interface clock 214 - const: mem 215 description: GPU Memory clock 216 - const: mem_iface 217 description: GPU Memory Interface clock 218 219 - if: 220 properties: 221 compatible: 222 contains: 223 pattern: '^qcom,adreno-405\.[0-9]+$' 224 then: 225 properties: 226 clocks: 227 minItems: 7 228 maxItems: 7 229 clock-names: 230 items: 231 - const: core 232 description: GPU Core clock 233 - const: iface 234 description: GPU Interface clock 235 - const: mem 236 description: GPU Memory clock 237 - const: mem_iface 238 description: GPU Memory Interface clock 239 - const: alt_mem_iface 240 description: GPU Alternative Memory Interface clock 241 - const: gfx3d 242 description: GPU 3D engine clock 243 - const: rbbmtimer 244 description: GPU RBBM Timer for Adreno 5xx series 245 246 - if: 247 properties: 248 compatible: 249 contains: 250 pattern: '^qcom,adreno-50[56]\.[0-9]+$' 251 then: 252 properties: 253 clocks: 254 minItems: 6 255 maxItems: 6 256 clock-names: 257 items: 258 - const: core 259 description: GPU Core clock 260 - const: iface 261 description: GPU Interface clock 262 - const: mem_iface 263 description: GPU Memory Interface clock 264 - const: alt_mem_iface 265 description: GPU Alternative Memory Interface clock 266 - const: rbbmtimer 267 description: GPU RBBM Timer for Adreno 5xx series 268 - const: alwayson 269 description: GPU AON clock 270 271 - if: 272 properties: 273 compatible: 274 contains: 275 oneOf: 276 - pattern: '^qcom,adreno-508\.[0-9]+$' 277 - pattern: '^qcom,adreno-509\.[0-9]+$' 278 - pattern: '^qcom,adreno-512\.[0-9]+$' 279 - pattern: '^qcom,adreno-540\.[0-9]+$' 280 then: 281 properties: 282 clocks: 283 minItems: 6 284 maxItems: 6 285 clock-names: 286 items: 287 - const: iface 288 description: GPU Interface clock 289 - const: rbbmtimer 290 description: GPU RBBM Timer for Adreno 5xx series 291 - const: mem 292 description: GPU Memory clock 293 - const: mem_iface 294 description: GPU Memory Interface clock 295 - const: rbcpr 296 description: GPU RB Core Power Reduction clock 297 - const: core 298 description: GPU Core clock 299 300 - if: 301 properties: 302 compatible: 303 contains: 304 pattern: '^qcom,adreno-510\.[0-9]+$' 305 then: 306 properties: 307 clocks: 308 minItems: 6 309 maxItems: 6 310 clock-names: 311 items: 312 - const: core 313 description: GPU Core clock 314 - const: iface 315 description: GPU Interface clock 316 - const: mem 317 description: GPU Memory clock 318 - const: mem_iface 319 description: GPU Memory Interface clock 320 - const: rbbmtimer 321 description: GPU RBBM Timer for Adreno 5xx series 322 - const: alwayson 323 description: GPU AON clock 324 325 - if: 326 properties: 327 compatible: 328 contains: 329 pattern: '^qcom,adreno-530\.[0-9]+$' 330 then: 331 properties: 332 clocks: 333 minItems: 5 334 maxItems: 5 335 clock-names: 336 items: 337 - const: core 338 description: GPU Core clock 339 - const: iface 340 description: GPU Interface clock 341 - const: rbbmtimer 342 description: GPU RBBM Timer for Adreno 5xx series 343 - const: mem 344 description: GPU Memory clock 345 - const: mem_iface 346 description: GPU Memory Interface clock 347 348 - if: 349 properties: 350 compatible: 351 contains: 352 enum: 353 - qcom,adreno-610.0 354 - qcom,adreno-619.1 355 - qcom,adreno-07000200 356 then: 357 properties: 358 clocks: 359 minItems: 6 360 maxItems: 6 361 362 clock-names: 363 items: 364 - const: core 365 description: GPU Core clock 366 - const: iface 367 description: GPU Interface clock 368 - const: mem_iface 369 description: GPU Memory Interface clock 370 - const: alt_mem_iface 371 description: GPU Alternative Memory Interface clock 372 - const: gmu 373 description: CX GMU clock 374 - const: xo 375 description: GPUCC clocksource clock 376 377 required: 378 - clocks 379 - clock-names 380 381 - if: 382 properties: 383 compatible: 384 contains: 385 const: qcom,adreno-612.0 386 then: 387 properties: 388 clocks: 389 items: 390 - description: GPU Core clock 391 392 clock-names: 393 items: 394 - const: core 395 396 reg: 397 minItems: 3 398 maxItems: 3 399 400 reg-names: 401 items: 402 - const: kgsl_3d0_reg_memory 403 - const: cx_mem 404 - const: cx_dbgc 405 406 required: 407 - clocks 408 - clock-names 409 410 - if: 411 properties: 412 compatible: 413 contains: 414 enum: 415 - qcom,adreno-44010000 416 - qcom,adreno-44070001 417 then: 418 properties: 419 reg: 420 minItems: 2 421 maxItems: 2 422 423 reg-names: 424 minItems: 2 425 maxItems: 2 426 427 - if: 428 properties: 429 compatible: 430 contains: 431 enum: 432 - qcom,adreno-615.0 433 - qcom,adreno-618.0 434 - qcom,adreno-619.0 435 - qcom,adreno-621.0 436 - qcom,adreno-623.0 437 - qcom,adreno-630.2 438 - qcom,adreno-635.0 439 - qcom,adreno-640.1 440 - qcom,adreno-650.2 441 - qcom,adreno-660.1 442 - qcom,adreno-663.0 443 - qcom,adreno-680.1 444 - qcom,adreno-690.0 445 - qcom,adreno-730.1 446 - qcom,adreno-43030c00 447 - qcom,adreno-43050a01 448 - qcom,adreno-43050c01 449 - qcom,adreno-43051401 450 - qcom,adreno-44010000 451 - qcom,adreno-44070001 452 453 then: # Starting with A6xx, the clocks are usually defined in the GMU node 454 properties: 455 clocks: false 456 clock-names: false 457 458examples: 459 - | 460 461 // Example a3xx/4xx: 462 463 #include <dt-bindings/clock/qcom,mmcc-msm8974.h> 464 #include <dt-bindings/clock/qcom,rpmcc.h> 465 #include <dt-bindings/interrupt-controller/irq.h> 466 #include <dt-bindings/interrupt-controller/arm-gic.h> 467 468 gpu: gpu@fdb00000 { 469 compatible = "qcom,adreno-330.2", "qcom,adreno"; 470 471 reg = <0xfdb00000 0x10000>; 472 reg-names = "kgsl_3d0_reg_memory"; 473 474 clock-names = "core", "iface", "mem_iface"; 475 clocks = <&mmcc OXILI_GFX3D_CLK>, 476 <&mmcc OXILICX_AHB_CLK>, 477 <&mmcc OXILICX_AXI_CLK>; 478 479 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 480 interrupt-names = "kgsl_3d0_irq"; 481 482 sram = <&gpu_sram>; 483 power-domains = <&mmcc OXILICX_GDSC>; 484 operating-points-v2 = <&gpu_opp_table>; 485 iommus = <&gpu_iommu 0>; 486 #cooling-cells = <2>; 487 }; 488 489 ocmem@fdd00000 { 490 compatible = "qcom,msm8974-ocmem"; 491 492 reg = <0xfdd00000 0x2000>, 493 <0xfec00000 0x180000>; 494 reg-names = "ctrl", "mem"; 495 496 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, 497 <&mmcc OCMEMCX_OCMEMNOC_CLK>; 498 clock-names = "core", "iface"; 499 500 #address-cells = <1>; 501 #size-cells = <1>; 502 ranges = <0 0xfec00000 0x100000>; 503 504 gpu_sram: gpu-sram@0 { 505 reg = <0x0 0x100000>; 506 }; 507 }; 508 - | 509 510 // Example a6xx (with GMU): 511 512 #include <dt-bindings/clock/qcom,gpucc-sdm845.h> 513 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 514 #include <dt-bindings/power/qcom-rpmpd.h> 515 #include <dt-bindings/interrupt-controller/irq.h> 516 #include <dt-bindings/interrupt-controller/arm-gic.h> 517 #include <dt-bindings/interconnect/qcom,sdm845.h> 518 519 reserved-memory { 520 #address-cells = <2>; 521 #size-cells = <2>; 522 523 zap_shader_region: gpu@8f200000 { 524 compatible = "shared-dma-pool"; 525 reg = <0x0 0x90b00000 0x0 0xa00000>; 526 no-map; 527 }; 528 }; 529 530 gpu@5000000 { 531 compatible = "qcom,adreno-630.2", "qcom,adreno"; 532 533 reg = <0x5000000 0x40000>, <0x509e000 0x10>; 534 reg-names = "kgsl_3d0_reg_memory", "cx_mem"; 535 536 #cooling-cells = <2>; 537 538 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 539 540 iommus = <&adreno_smmu 0>; 541 542 operating-points-v2 = <&gpu_opp_table>; 543 544 interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>; 545 interconnect-names = "gfx-mem"; 546 547 qcom,gmu = <&gmu>; 548 549 gpu_opp_table: opp-table { 550 compatible = "operating-points-v2"; 551 552 opp-430000000 { 553 opp-hz = /bits/ 64 <430000000>; 554 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 555 opp-peak-kBps = <5412000>; 556 }; 557 558 opp-355000000 { 559 opp-hz = /bits/ 64 <355000000>; 560 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 561 opp-peak-kBps = <3072000>; 562 }; 563 564 opp-267000000 { 565 opp-hz = /bits/ 64 <267000000>; 566 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 567 opp-peak-kBps = <3072000>; 568 }; 569 570 opp-180000000 { 571 opp-hz = /bits/ 64 <180000000>; 572 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 573 opp-peak-kBps = <1804000>; 574 }; 575 }; 576 577 zap-shader { 578 memory-region = <&zap_shader_region>; 579 firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn"; 580 }; 581 }; 582