1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4 5$id: http://devicetree.org/schemas/display/msm/gpu.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: Adreno or Snapdragon GPUs 9 10maintainers: 11 - Rob Clark <robdclark@gmail.com> 12 13# dtschema does not select nodes based on pattern+const, so add custom select 14# as a work-around: 15select: 16 properties: 17 compatible: 18 contains: 19 enum: 20 - qcom,adreno 21 - amd,imageon 22 required: 23 - compatible 24 25properties: 26 compatible: 27 oneOf: 28 - description: | 29 The driver is parsing the compat string for Adreno to 30 figure out the chip-id. 31 items: 32 - pattern: '^qcom,adreno-[0-9a-f]{8}$' 33 - const: qcom,adreno 34 - description: | 35 The driver is parsing the compat string for Adreno to 36 figure out the gpu-id and patch level. 37 items: 38 - pattern: '^qcom,adreno-[3-7][0-9][0-9]\.[0-9]+$' 39 - const: qcom,adreno 40 - description: | 41 The driver is parsing the compat string for Imageon to 42 figure out the gpu-id and patch level. 43 items: 44 - pattern: '^amd,imageon-200\.[0-1]$' 45 - const: amd,imageon 46 47 clocks: 48 minItems: 2 49 maxItems: 7 50 51 clock-names: 52 minItems: 2 53 maxItems: 7 54 55 reg: 56 minItems: 1 57 maxItems: 3 58 59 reg-names: 60 minItems: 1 61 items: 62 - const: kgsl_3d0_reg_memory 63 - const: cx_mem 64 - const: cx_dbgc 65 66 interrupts: 67 maxItems: 1 68 69 interrupt-names: 70 maxItems: 1 71 72 interconnects: 73 minItems: 1 74 maxItems: 2 75 76 interconnect-names: 77 minItems: 1 78 items: 79 - const: gfx-mem 80 - const: ocmem 81 82 iommus: 83 minItems: 1 84 maxItems: 64 85 86 sram: 87 $ref: /schemas/types.yaml#/definitions/phandle-array 88 minItems: 1 89 maxItems: 4 90 items: 91 maxItems: 1 92 description: | 93 phandles to one or more reserved on-chip SRAM regions. 94 phandle to the On Chip Memory (OCMEM) that's present on some a3xx and 95 a4xx Snapdragon SoCs. See 96 Documentation/devicetree/bindings/sram/qcom,ocmem.yaml 97 98 operating-points-v2: true 99 opp-table: 100 type: object 101 102 power-domains: 103 maxItems: 1 104 105 zap-shader: 106 type: object 107 additionalProperties: false 108 description: | 109 For a5xx and a6xx devices this node contains a memory-region that 110 points to reserved memory to store the zap shader that can be used to 111 help bring the GPU out of secure mode. 112 properties: 113 memory-region: 114 maxItems: 1 115 116 firmware-name: 117 description: | 118 Default name of the firmware to load to the remote processor. 119 120 "#cooling-cells": 121 const: 2 122 123 nvmem-cell-names: 124 maxItems: 1 125 126 nvmem-cells: 127 description: efuse registers 128 maxItems: 1 129 130 qcom,gmu: 131 $ref: /schemas/types.yaml#/definitions/phandle 132 description: | 133 For GMU attached devices a phandle to the GMU device that will 134 control the power for the GPU. 135 136 137required: 138 - compatible 139 - reg 140 - interrupts 141 142additionalProperties: false 143 144allOf: 145 - if: 146 properties: 147 compatible: 148 contains: 149 pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]+$' 150 151 then: 152 properties: 153 clocks: 154 minItems: 2 155 maxItems: 7 156 157 clock-names: 158 items: 159 anyOf: 160 - const: core 161 description: GPU Core clock 162 - const: iface 163 description: GPU Interface clock 164 - const: mem 165 description: GPU Memory clock 166 - const: mem_iface 167 description: GPU Memory Interface clock 168 - const: alt_mem_iface 169 description: GPU Alternative Memory Interface clock 170 - const: gfx3d 171 description: GPU 3D engine clock 172 - const: rbbmtimer 173 description: GPU RBBM Timer for Adreno 5xx series 174 - const: rbcpr 175 description: GPU RB Core Power Reduction clock 176 minItems: 2 177 maxItems: 7 178 179 required: 180 - clocks 181 - clock-names 182 183 - if: 184 properties: 185 compatible: 186 contains: 187 enum: 188 - qcom,adreno-610.0 189 - qcom,adreno-619.1 190 then: 191 properties: 192 clocks: 193 minItems: 6 194 maxItems: 6 195 196 clock-names: 197 items: 198 - const: core 199 description: GPU Core clock 200 - const: iface 201 description: GPU Interface clock 202 - const: mem_iface 203 description: GPU Memory Interface clock 204 - const: alt_mem_iface 205 description: GPU Alternative Memory Interface clock 206 - const: gmu 207 description: CX GMU clock 208 - const: xo 209 description: GPUCC clocksource clock 210 211 reg-names: 212 minItems: 1 213 items: 214 - const: kgsl_3d0_reg_memory 215 - const: cx_dbgc 216 217 required: 218 - clocks 219 - clock-names 220 else: 221 if: 222 properties: 223 compatible: 224 contains: 225 pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]+$' 226 227 then: # Starting with A6xx, the clocks are usually defined in the GMU node 228 properties: 229 clocks: false 230 clock-names: false 231 232 reg-names: 233 minItems: 1 234 items: 235 - const: kgsl_3d0_reg_memory 236 - const: cx_mem 237 - const: cx_dbgc 238 239examples: 240 - | 241 242 // Example a3xx/4xx: 243 244 #include <dt-bindings/clock/qcom,mmcc-msm8974.h> 245 #include <dt-bindings/clock/qcom,rpmcc.h> 246 #include <dt-bindings/interrupt-controller/irq.h> 247 #include <dt-bindings/interrupt-controller/arm-gic.h> 248 249 gpu: gpu@fdb00000 { 250 compatible = "qcom,adreno-330.2", "qcom,adreno"; 251 252 reg = <0xfdb00000 0x10000>; 253 reg-names = "kgsl_3d0_reg_memory"; 254 255 clock-names = "core", "iface", "mem_iface"; 256 clocks = <&mmcc OXILI_GFX3D_CLK>, 257 <&mmcc OXILICX_AHB_CLK>, 258 <&mmcc OXILICX_AXI_CLK>; 259 260 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 261 interrupt-names = "kgsl_3d0_irq"; 262 263 sram = <&gpu_sram>; 264 power-domains = <&mmcc OXILICX_GDSC>; 265 operating-points-v2 = <&gpu_opp_table>; 266 iommus = <&gpu_iommu 0>; 267 #cooling-cells = <2>; 268 }; 269 270 ocmem@fdd00000 { 271 compatible = "qcom,msm8974-ocmem"; 272 273 reg = <0xfdd00000 0x2000>, 274 <0xfec00000 0x180000>; 275 reg-names = "ctrl", "mem"; 276 277 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, 278 <&mmcc OCMEMCX_OCMEMNOC_CLK>; 279 clock-names = "core", "iface"; 280 281 #address-cells = <1>; 282 #size-cells = <1>; 283 ranges = <0 0xfec00000 0x100000>; 284 285 gpu_sram: gpu-sram@0 { 286 reg = <0x0 0x100000>; 287 }; 288 }; 289 - | 290 291 // Example a6xx (with GMU): 292 293 #include <dt-bindings/clock/qcom,gpucc-sdm845.h> 294 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 295 #include <dt-bindings/power/qcom-rpmpd.h> 296 #include <dt-bindings/interrupt-controller/irq.h> 297 #include <dt-bindings/interrupt-controller/arm-gic.h> 298 #include <dt-bindings/interconnect/qcom,sdm845.h> 299 300 reserved-memory { 301 #address-cells = <2>; 302 #size-cells = <2>; 303 304 zap_shader_region: gpu@8f200000 { 305 compatible = "shared-dma-pool"; 306 reg = <0x0 0x90b00000 0x0 0xa00000>; 307 no-map; 308 }; 309 }; 310 311 gpu@5000000 { 312 compatible = "qcom,adreno-630.2", "qcom,adreno"; 313 314 reg = <0x5000000 0x40000>, <0x509e000 0x10>; 315 reg-names = "kgsl_3d0_reg_memory", "cx_mem"; 316 317 #cooling-cells = <2>; 318 319 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 320 321 iommus = <&adreno_smmu 0>; 322 323 operating-points-v2 = <&gpu_opp_table>; 324 325 interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>; 326 interconnect-names = "gfx-mem"; 327 328 qcom,gmu = <&gmu>; 329 330 gpu_opp_table: opp-table { 331 compatible = "operating-points-v2"; 332 333 opp-430000000 { 334 opp-hz = /bits/ 64 <430000000>; 335 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 336 opp-peak-kBps = <5412000>; 337 }; 338 339 opp-355000000 { 340 opp-hz = /bits/ 64 <355000000>; 341 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 342 opp-peak-kBps = <3072000>; 343 }; 344 345 opp-267000000 { 346 opp-hz = /bits/ 64 <267000000>; 347 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 348 opp-peak-kBps = <3072000>; 349 }; 350 351 opp-180000000 { 352 opp-hz = /bits/ 64 <180000000>; 353 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 354 opp-peak-kBps = <1804000>; 355 }; 356 }; 357 358 zap-shader { 359 memory-region = <&zap_shader_region>; 360 firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn"; 361 }; 362 }; 363