1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4 5$id: "http://devicetree.org/schemas/display/msm/gpu.yaml#" 6$schema: "http://devicetree.org/meta-schemas/core.yaml#" 7 8title: Devicetree bindings for the Adreno or Snapdragon GPUs 9 10maintainers: 11 - Rob Clark <robdclark@gmail.com> 12 13properties: 14 compatible: 15 oneOf: 16 - description: | 17 The driver is parsing the compat string for Adreno to 18 figure out the gpu-id and patch level. 19 items: 20 - pattern: '^qcom,adreno-[3-6][0-9][0-9]\.[0-9]$' 21 - const: qcom,adreno 22 - description: | 23 The driver is parsing the compat string for Imageon to 24 figure out the gpu-id and patch level. 25 items: 26 - pattern: '^amd,imageon-200\.[0-1]$' 27 - const: amd,imageon 28 29 clocks: true 30 31 clock-names: true 32 33 reg: 34 minItems: 1 35 maxItems: 3 36 37 reg-names: 38 minItems: 1 39 items: 40 - const: kgsl_3d0_reg_memory 41 - const: cx_mem 42 - const: cx_dbgc 43 44 interrupts: 45 maxItems: 1 46 47 interrupt-names: 48 maxItems: 1 49 50 interconnects: 51 minItems: 1 52 maxItems: 2 53 54 interconnect-names: 55 minItems: 1 56 items: 57 - const: gfx-mem 58 - const: ocmem 59 60 iommus: 61 maxItems: 1 62 63 sram: 64 $ref: /schemas/types.yaml#/definitions/phandle-array 65 minItems: 1 66 maxItems: 4 67 items: 68 maxItems: 1 69 description: | 70 phandles to one or more reserved on-chip SRAM regions. 71 phandle to the On Chip Memory (OCMEM) that's present on some a3xx and 72 a4xx Snapdragon SoCs. See 73 Documentation/devicetree/bindings/sram/qcom,ocmem.yaml 74 75 operating-points-v2: true 76 opp-table: 77 type: object 78 79 power-domains: 80 maxItems: 1 81 82 zap-shader: 83 type: object 84 additionalProperties: false 85 description: | 86 For a5xx and a6xx devices this node contains a memory-region that 87 points to reserved memory to store the zap shader that can be used to 88 help bring the GPU out of secure mode. 89 properties: 90 memory-region: 91 $ref: /schemas/types.yaml#/definitions/phandle 92 93 firmware-name: 94 description: | 95 Default name of the firmware to load to the remote processor. 96 97 "#cooling-cells": 98 const: 2 99 100 nvmem-cell-names: 101 maxItems: 1 102 103 nvmem-cells: 104 description: efuse registers 105 maxItems: 1 106 107 qcom,gmu: 108 $ref: /schemas/types.yaml#/definitions/phandle 109 description: | 110 For GMU attached devices a phandle to the GMU device that will 111 control the power for the GPU. 112 113 114required: 115 - compatible 116 - reg 117 - interrupts 118 119additionalProperties: false 120 121allOf: 122 - if: 123 properties: 124 compatible: 125 contains: 126 pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]$' 127 128 then: 129 properties: 130 clocks: 131 minItems: 2 132 maxItems: 7 133 134 clock-names: 135 items: 136 anyOf: 137 - const: core 138 description: GPU Core clock 139 - const: iface 140 description: GPU Interface clock 141 - const: mem 142 description: GPU Memory clock 143 - const: mem_iface 144 description: GPU Memory Interface clock 145 - const: alt_mem_iface 146 description: GPU Alternative Memory Interface clock 147 - const: gfx3d 148 description: GPU 3D engine clock 149 - const: rbbmtimer 150 description: GPU RBBM Timer for Adreno 5xx series 151 minItems: 2 152 maxItems: 7 153 154 required: 155 - clocks 156 - clock-names 157 - if: 158 properties: 159 compatible: 160 contains: 161 pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$' 162 163 then: # Since Adreno 6xx series clocks should be defined in GMU 164 properties: 165 clocks: false 166 clock-names: false 167 168examples: 169 - | 170 171 // Example a3xx/4xx: 172 173 #include <dt-bindings/clock/qcom,mmcc-msm8974.h> 174 #include <dt-bindings/clock/qcom,rpmcc.h> 175 #include <dt-bindings/interrupt-controller/irq.h> 176 #include <dt-bindings/interrupt-controller/arm-gic.h> 177 178 gpu: gpu@fdb00000 { 179 compatible = "qcom,adreno-330.2", "qcom,adreno"; 180 181 reg = <0xfdb00000 0x10000>; 182 reg-names = "kgsl_3d0_reg_memory"; 183 184 clock-names = "core", "iface", "mem_iface"; 185 clocks = <&mmcc OXILI_GFX3D_CLK>, 186 <&mmcc OXILICX_AHB_CLK>, 187 <&mmcc OXILICX_AXI_CLK>; 188 189 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 190 interrupt-names = "kgsl_3d0_irq"; 191 192 sram = <&gpu_sram>; 193 power-domains = <&mmcc OXILICX_GDSC>; 194 operating-points-v2 = <&gpu_opp_table>; 195 iommus = <&gpu_iommu 0>; 196 #cooling-cells = <2>; 197 }; 198 199 ocmem@fdd00000 { 200 compatible = "qcom,msm8974-ocmem"; 201 202 reg = <0xfdd00000 0x2000>, 203 <0xfec00000 0x180000>; 204 reg-names = "ctrl", "mem"; 205 206 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, 207 <&mmcc OCMEMCX_OCMEMNOC_CLK>; 208 clock-names = "core", "iface"; 209 210 #address-cells = <1>; 211 #size-cells = <1>; 212 ranges = <0 0xfec00000 0x100000>; 213 214 gpu_sram: gpu-sram@0 { 215 reg = <0x0 0x100000>; 216 }; 217 }; 218 - | 219 220 // Example a6xx (with GMU): 221 222 #include <dt-bindings/clock/qcom,gpucc-sdm845.h> 223 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 224 #include <dt-bindings/power/qcom-rpmpd.h> 225 #include <dt-bindings/interrupt-controller/irq.h> 226 #include <dt-bindings/interrupt-controller/arm-gic.h> 227 #include <dt-bindings/interconnect/qcom,sdm845.h> 228 229 reserved-memory { 230 #address-cells = <2>; 231 #size-cells = <2>; 232 233 zap_shader_region: gpu@8f200000 { 234 compatible = "shared-dma-pool"; 235 reg = <0x0 0x90b00000 0x0 0xa00000>; 236 no-map; 237 }; 238 }; 239 240 gpu@5000000 { 241 compatible = "qcom,adreno-630.2", "qcom,adreno"; 242 243 reg = <0x5000000 0x40000>, <0x509e000 0x10>; 244 reg-names = "kgsl_3d0_reg_memory", "cx_mem"; 245 246 #cooling-cells = <2>; 247 248 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 249 250 iommus = <&adreno_smmu 0>; 251 252 operating-points-v2 = <&gpu_opp_table>; 253 254 interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>; 255 interconnect-names = "gfx-mem"; 256 257 qcom,gmu = <&gmu>; 258 259 gpu_opp_table: opp-table { 260 compatible = "operating-points-v2"; 261 262 opp-430000000 { 263 opp-hz = /bits/ 64 <430000000>; 264 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 265 opp-peak-kBps = <5412000>; 266 }; 267 268 opp-355000000 { 269 opp-hz = /bits/ 64 <355000000>; 270 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 271 opp-peak-kBps = <3072000>; 272 }; 273 274 opp-267000000 { 275 opp-hz = /bits/ 64 <267000000>; 276 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 277 opp-peak-kBps = <3072000>; 278 }; 279 280 opp-180000000 { 281 opp-hz = /bits/ 64 <180000000>; 282 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 283 opp-peak-kBps = <1804000>; 284 }; 285 }; 286 287 zap-shader { 288 memory-region = <&zap_shader_region>; 289 firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn"; 290 }; 291 }; 292