1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4 5$id: http://devicetree.org/schemas/display/msm/gpu.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: Adreno or Snapdragon GPUs 9 10maintainers: 11 - Rob Clark <robdclark@gmail.com> 12 13# dtschema does not select nodes based on pattern+const, so add custom select 14# as a work-around: 15select: 16 properties: 17 compatible: 18 contains: 19 enum: 20 - qcom,adreno 21 - amd,imageon 22 required: 23 - compatible 24 25properties: 26 compatible: 27 oneOf: 28 - description: | 29 The driver is parsing the compat string for Adreno to 30 figure out the chip-id. 31 items: 32 - pattern: '^qcom,adreno-[0-9a-f]{8}$' 33 - const: qcom,adreno 34 - description: | 35 The driver is parsing the compat string for Adreno to 36 figure out the gpu-id and patch level. 37 items: 38 - pattern: '^qcom,adreno-[3-7][0-9][0-9]\.[0-9]+$' 39 - const: qcom,adreno 40 - description: | 41 The driver is parsing the compat string for Imageon to 42 figure out the gpu-id and patch level. 43 items: 44 - pattern: '^amd,imageon-200\.[0-1]$' 45 - const: amd,imageon 46 47 clocks: 48 minItems: 2 49 maxItems: 7 50 51 clock-names: 52 minItems: 2 53 maxItems: 7 54 55 reg: 56 minItems: 1 57 maxItems: 3 58 59 reg-names: 60 minItems: 1 61 items: 62 - const: kgsl_3d0_reg_memory 63 - const: cx_mem 64 - const: cx_dbgc 65 66 interrupts: 67 maxItems: 1 68 69 interrupt-names: 70 maxItems: 1 71 72 interconnects: 73 minItems: 1 74 maxItems: 2 75 76 interconnect-names: 77 minItems: 1 78 items: 79 - const: gfx-mem 80 - const: ocmem 81 82 iommus: 83 minItems: 1 84 maxItems: 64 85 86 sram: 87 $ref: /schemas/types.yaml#/definitions/phandle-array 88 minItems: 1 89 maxItems: 4 90 items: 91 maxItems: 1 92 description: | 93 phandles to one or more reserved on-chip SRAM regions. 94 phandle to the On Chip Memory (OCMEM) that's present on some a3xx and 95 a4xx Snapdragon SoCs. See 96 Documentation/devicetree/bindings/sram/qcom,ocmem.yaml 97 98 operating-points-v2: true 99 opp-table: 100 type: object 101 102 power-domains: 103 maxItems: 1 104 105 zap-shader: 106 type: object 107 additionalProperties: false 108 description: | 109 For a5xx and a6xx devices this node contains a memory-region that 110 points to reserved memory to store the zap shader that can be used to 111 help bring the GPU out of secure mode. 112 properties: 113 memory-region: 114 maxItems: 1 115 116 firmware-name: 117 description: | 118 Default name of the firmware to load to the remote processor. 119 120 "#cooling-cells": 121 const: 2 122 123 nvmem-cell-names: 124 maxItems: 1 125 126 nvmem-cells: 127 description: efuse registers 128 maxItems: 1 129 130 qcom,gmu: 131 $ref: /schemas/types.yaml#/definitions/phandle 132 description: | 133 For GMU attached devices a phandle to the GMU device that will 134 control the power for the GPU. 135 136 137required: 138 - compatible 139 - reg 140 - interrupts 141 142additionalProperties: false 143 144allOf: 145 - if: 146 properties: 147 compatible: 148 contains: 149 oneOf: 150 - pattern: '^qcom,adreno-305\.[0-9]+$' 151 - pattern: '^qcom,adreno-330\.[0-9]+$' 152 then: 153 properties: 154 clocks: 155 minItems: 3 156 maxItems: 3 157 clock-names: 158 items: 159 - const: core 160 description: GPU Core clock 161 - const: iface 162 description: GPU Interface clock 163 - const: mem_iface 164 description: GPU Memory Interface clock 165 166 - if: 167 properties: 168 compatible: 169 contains: 170 pattern: '^qcom,adreno-306\.[0-9]+$' 171 then: 172 properties: 173 clocks: 174 minItems: 5 175 maxItems: 6 176 clock-names: 177 oneOf: 178 - items: 179 - const: core 180 description: GPU Core clock 181 - const: iface 182 description: GPU Interface clock 183 - const: mem_iface 184 description: GPU Memory Interface clock 185 - const: alt_mem_iface 186 description: GPU Alternative Memory Interface clock 187 - const: gfx3d 188 description: GPU 3D engine clock 189 - items: 190 - const: core 191 description: GPU Core clock 192 - const: iface 193 description: GPU Interface clock 194 - const: mem 195 description: GPU Memory clock 196 - const: mem_iface 197 description: GPU Memory Interface clock 198 - const: alt_mem_iface 199 description: GPU Alternative Memory Interface clock 200 - const: gfx3d 201 description: GPU 3D engine clock 202 203 - if: 204 properties: 205 compatible: 206 contains: 207 pattern: '^qcom,adreno-320\.[0-9]+$' 208 then: 209 properties: 210 clocks: 211 minItems: 4 212 maxItems: 4 213 clock-names: 214 items: 215 - const: core 216 description: GPU Core clock 217 - const: iface 218 description: GPU Interface clock 219 - const: mem 220 description: GPU Memory clock 221 - const: mem_iface 222 description: GPU Memory Interface clock 223 224 - if: 225 properties: 226 compatible: 227 contains: 228 pattern: '^qcom,adreno-405\.[0-9]+$' 229 then: 230 properties: 231 clocks: 232 minItems: 7 233 maxItems: 7 234 clock-names: 235 items: 236 - const: core 237 description: GPU Core clock 238 - const: iface 239 description: GPU Interface clock 240 - const: mem 241 description: GPU Memory clock 242 - const: mem_iface 243 description: GPU Memory Interface clock 244 - const: alt_mem_iface 245 description: GPU Alternative Memory Interface clock 246 - const: gfx3d 247 description: GPU 3D engine clock 248 - const: rbbmtimer 249 description: GPU RBBM Timer for Adreno 5xx series 250 251 - if: 252 properties: 253 compatible: 254 contains: 255 pattern: '^qcom,adreno-50[56]\.[0-9]+$' 256 then: 257 properties: 258 clocks: 259 minItems: 6 260 maxItems: 6 261 clock-names: 262 items: 263 - const: core 264 description: GPU Core clock 265 - const: iface 266 description: GPU Interface clock 267 - const: mem_iface 268 description: GPU Memory Interface clock 269 - const: alt_mem_iface 270 description: GPU Alternative Memory Interface clock 271 - const: rbbmtimer 272 description: GPU RBBM Timer for Adreno 5xx series 273 - const: alwayson 274 description: GPU AON clock 275 276 - if: 277 properties: 278 compatible: 279 contains: 280 oneOf: 281 - pattern: '^qcom,adreno-508\.[0-9]+$' 282 - pattern: '^qcom,adreno-509\.[0-9]+$' 283 - pattern: '^qcom,adreno-512\.[0-9]+$' 284 - pattern: '^qcom,adreno-540\.[0-9]+$' 285 then: 286 properties: 287 clocks: 288 minItems: 6 289 maxItems: 6 290 clock-names: 291 items: 292 - const: iface 293 description: GPU Interface clock 294 - const: rbbmtimer 295 description: GPU RBBM Timer for Adreno 5xx series 296 - const: mem 297 description: GPU Memory clock 298 - const: mem_iface 299 description: GPU Memory Interface clock 300 - const: rbcpr 301 description: GPU RB Core Power Reduction clock 302 - const: core 303 description: GPU Core clock 304 305 - if: 306 properties: 307 compatible: 308 contains: 309 pattern: '^qcom,adreno-510\.[0-9]+$' 310 then: 311 properties: 312 clocks: 313 minItems: 6 314 maxItems: 6 315 clock-names: 316 items: 317 - const: core 318 description: GPU Core clock 319 - const: iface 320 description: GPU Interface clock 321 - const: mem 322 description: GPU Memory clock 323 - const: mem_iface 324 description: GPU Memory Interface clock 325 - const: rbbmtimer 326 description: GPU RBBM Timer for Adreno 5xx series 327 - const: alwayson 328 description: GPU AON clock 329 330 - if: 331 properties: 332 compatible: 333 contains: 334 pattern: '^qcom,adreno-530\.[0-9]+$' 335 then: 336 properties: 337 clocks: 338 minItems: 5 339 maxItems: 5 340 clock-names: 341 items: 342 - const: core 343 description: GPU Core clock 344 - const: iface 345 description: GPU Interface clock 346 - const: rbbmtimer 347 description: GPU RBBM Timer for Adreno 5xx series 348 - const: mem 349 description: GPU Memory clock 350 - const: mem_iface 351 description: GPU Memory Interface clock 352 353 - if: 354 properties: 355 compatible: 356 contains: 357 enum: 358 - qcom,adreno-610.0 359 - qcom,adreno-619.1 360 - qcom,adreno-07000200 361 then: 362 properties: 363 clocks: 364 minItems: 6 365 maxItems: 6 366 367 clock-names: 368 items: 369 - const: core 370 description: GPU Core clock 371 - const: iface 372 description: GPU Interface clock 373 - const: mem_iface 374 description: GPU Memory Interface clock 375 - const: alt_mem_iface 376 description: GPU Alternative Memory Interface clock 377 - const: gmu 378 description: CX GMU clock 379 - const: xo 380 description: GPUCC clocksource clock 381 382 reg-names: 383 minItems: 1 384 items: 385 - const: kgsl_3d0_reg_memory 386 - const: cx_dbgc 387 388 required: 389 - clocks 390 - clock-names 391 else: 392 if: 393 properties: 394 compatible: 395 contains: 396 oneOf: 397 - pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]+$' 398 - pattern: '^qcom,adreno-[0-9a-f]{8}$' 399 400 then: # Starting with A6xx, the clocks are usually defined in the GMU node 401 properties: 402 clocks: false 403 clock-names: false 404 405 reg-names: 406 minItems: 1 407 items: 408 - const: kgsl_3d0_reg_memory 409 - const: cx_mem 410 - const: cx_dbgc 411 412examples: 413 - | 414 415 // Example a3xx/4xx: 416 417 #include <dt-bindings/clock/qcom,mmcc-msm8974.h> 418 #include <dt-bindings/clock/qcom,rpmcc.h> 419 #include <dt-bindings/interrupt-controller/irq.h> 420 #include <dt-bindings/interrupt-controller/arm-gic.h> 421 422 gpu: gpu@fdb00000 { 423 compatible = "qcom,adreno-330.2", "qcom,adreno"; 424 425 reg = <0xfdb00000 0x10000>; 426 reg-names = "kgsl_3d0_reg_memory"; 427 428 clock-names = "core", "iface", "mem_iface"; 429 clocks = <&mmcc OXILI_GFX3D_CLK>, 430 <&mmcc OXILICX_AHB_CLK>, 431 <&mmcc OXILICX_AXI_CLK>; 432 433 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 434 interrupt-names = "kgsl_3d0_irq"; 435 436 sram = <&gpu_sram>; 437 power-domains = <&mmcc OXILICX_GDSC>; 438 operating-points-v2 = <&gpu_opp_table>; 439 iommus = <&gpu_iommu 0>; 440 #cooling-cells = <2>; 441 }; 442 443 ocmem@fdd00000 { 444 compatible = "qcom,msm8974-ocmem"; 445 446 reg = <0xfdd00000 0x2000>, 447 <0xfec00000 0x180000>; 448 reg-names = "ctrl", "mem"; 449 450 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, 451 <&mmcc OCMEMCX_OCMEMNOC_CLK>; 452 clock-names = "core", "iface"; 453 454 #address-cells = <1>; 455 #size-cells = <1>; 456 ranges = <0 0xfec00000 0x100000>; 457 458 gpu_sram: gpu-sram@0 { 459 reg = <0x0 0x100000>; 460 }; 461 }; 462 - | 463 464 // Example a6xx (with GMU): 465 466 #include <dt-bindings/clock/qcom,gpucc-sdm845.h> 467 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 468 #include <dt-bindings/power/qcom-rpmpd.h> 469 #include <dt-bindings/interrupt-controller/irq.h> 470 #include <dt-bindings/interrupt-controller/arm-gic.h> 471 #include <dt-bindings/interconnect/qcom,sdm845.h> 472 473 reserved-memory { 474 #address-cells = <2>; 475 #size-cells = <2>; 476 477 zap_shader_region: gpu@8f200000 { 478 compatible = "shared-dma-pool"; 479 reg = <0x0 0x90b00000 0x0 0xa00000>; 480 no-map; 481 }; 482 }; 483 484 gpu@5000000 { 485 compatible = "qcom,adreno-630.2", "qcom,adreno"; 486 487 reg = <0x5000000 0x40000>, <0x509e000 0x10>; 488 reg-names = "kgsl_3d0_reg_memory", "cx_mem"; 489 490 #cooling-cells = <2>; 491 492 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 493 494 iommus = <&adreno_smmu 0>; 495 496 operating-points-v2 = <&gpu_opp_table>; 497 498 interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>; 499 interconnect-names = "gfx-mem"; 500 501 qcom,gmu = <&gmu>; 502 503 gpu_opp_table: opp-table { 504 compatible = "operating-points-v2"; 505 506 opp-430000000 { 507 opp-hz = /bits/ 64 <430000000>; 508 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 509 opp-peak-kBps = <5412000>; 510 }; 511 512 opp-355000000 { 513 opp-hz = /bits/ 64 <355000000>; 514 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 515 opp-peak-kBps = <3072000>; 516 }; 517 518 opp-267000000 { 519 opp-hz = /bits/ 64 <267000000>; 520 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 521 opp-peak-kBps = <3072000>; 522 }; 523 524 opp-180000000 { 525 opp-hz = /bits/ 64 <180000000>; 526 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 527 opp-peak-kBps = <1804000>; 528 }; 529 }; 530 531 zap-shader { 532 memory-region = <&zap_shader_region>; 533 firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn"; 534 }; 535 }; 536