1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4 5$id: http://devicetree.org/schemas/display/msm/gpu.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: Adreno or Snapdragon GPUs 9 10maintainers: 11 - Rob Clark <robdclark@gmail.com> 12 13# dtschema does not select nodes based on pattern+const, so add custom select 14# as a work-around: 15select: 16 properties: 17 compatible: 18 contains: 19 enum: 20 - qcom,adreno 21 - amd,imageon 22 required: 23 - compatible 24 25properties: 26 compatible: 27 oneOf: 28 - description: | 29 The driver is parsing the compat string for Adreno to 30 figure out the chip-id. 31 items: 32 - pattern: '^qcom,adreno-[0-9a-f]{8}$' 33 - const: qcom,adreno 34 - description: | 35 The driver is parsing the compat string for Adreno to 36 figure out the gpu-id and patch level. 37 items: 38 - pattern: '^qcom,adreno-[3-7][0-9][0-9]\.[0-9]+$' 39 - const: qcom,adreno 40 - description: | 41 The driver is parsing the compat string for Imageon to 42 figure out the gpu-id and patch level. 43 items: 44 - pattern: '^amd,imageon-200\.[0-1]$' 45 - const: amd,imageon 46 47 clocks: 48 minItems: 1 49 maxItems: 7 50 51 clock-names: 52 minItems: 1 53 maxItems: 7 54 55 reg: 56 minItems: 1 57 maxItems: 3 58 59 reg-names: 60 minItems: 1 61 items: 62 - const: kgsl_3d0_reg_memory 63 - const: cx_mem 64 - const: cx_dbgc 65 66 interrupts: 67 maxItems: 1 68 69 interrupt-names: 70 maxItems: 1 71 72 interconnects: 73 minItems: 1 74 maxItems: 2 75 76 interconnect-names: 77 minItems: 1 78 items: 79 - const: gfx-mem 80 - const: ocmem 81 82 iommus: 83 minItems: 1 84 maxItems: 64 85 86 sram: 87 $ref: /schemas/types.yaml#/definitions/phandle-array 88 minItems: 1 89 maxItems: 4 90 items: 91 maxItems: 1 92 description: | 93 phandles to one or more reserved on-chip SRAM regions. 94 phandle to the On Chip Memory (OCMEM) that's present on some a3xx and 95 a4xx Snapdragon SoCs. See 96 Documentation/devicetree/bindings/sram/qcom,ocmem.yaml 97 98 operating-points-v2: true 99 opp-table: 100 type: object 101 102 power-domains: 103 maxItems: 1 104 105 zap-shader: 106 type: object 107 additionalProperties: false 108 description: | 109 For a5xx and a6xx devices this node contains a memory-region that 110 points to reserved memory to store the zap shader that can be used to 111 help bring the GPU out of secure mode. 112 properties: 113 memory-region: 114 maxItems: 1 115 116 firmware-name: 117 description: | 118 Default name of the firmware to load to the remote processor. 119 120 "#cooling-cells": 121 const: 2 122 123 nvmem-cell-names: 124 maxItems: 1 125 126 nvmem-cells: 127 description: efuse registers 128 maxItems: 1 129 130 qcom,gmu: 131 $ref: /schemas/types.yaml#/definitions/phandle 132 description: | 133 For GMU attached devices a phandle to the GMU device that will 134 control the power for the GPU. 135 136required: 137 - compatible 138 - reg 139 - interrupts 140 141additionalProperties: false 142 143allOf: 144 - if: 145 properties: 146 compatible: 147 contains: 148 oneOf: 149 - pattern: '^qcom,adreno-305\.[0-9]+$' 150 - pattern: '^qcom,adreno-330\.[0-9]+$' 151 then: 152 properties: 153 clocks: 154 minItems: 3 155 maxItems: 3 156 clock-names: 157 items: 158 - const: core 159 description: GPU Core clock 160 - const: iface 161 description: GPU Interface clock 162 - const: mem_iface 163 description: GPU Memory Interface clock 164 165 - if: 166 properties: 167 compatible: 168 contains: 169 pattern: '^qcom,adreno-306\.[0-9]+$' 170 then: 171 properties: 172 clocks: 173 minItems: 5 174 maxItems: 6 175 clock-names: 176 oneOf: 177 - items: 178 - const: core 179 description: GPU Core clock 180 - const: iface 181 description: GPU Interface clock 182 - const: mem_iface 183 description: GPU Memory Interface clock 184 - const: alt_mem_iface 185 description: GPU Alternative Memory Interface clock 186 - const: gfx3d 187 description: GPU 3D engine clock 188 - items: 189 - const: core 190 description: GPU Core clock 191 - const: iface 192 description: GPU Interface clock 193 - const: mem 194 description: GPU Memory clock 195 - const: mem_iface 196 description: GPU Memory Interface clock 197 - const: alt_mem_iface 198 description: GPU Alternative Memory Interface clock 199 - const: gfx3d 200 description: GPU 3D engine clock 201 202 - if: 203 properties: 204 compatible: 205 contains: 206 pattern: '^qcom,adreno-320\.[0-9]+$' 207 then: 208 properties: 209 clocks: 210 minItems: 4 211 maxItems: 4 212 clock-names: 213 items: 214 - const: core 215 description: GPU Core clock 216 - const: iface 217 description: GPU Interface clock 218 - const: mem 219 description: GPU Memory clock 220 - const: mem_iface 221 description: GPU Memory Interface clock 222 223 - if: 224 properties: 225 compatible: 226 contains: 227 pattern: '^qcom,adreno-405\.[0-9]+$' 228 then: 229 properties: 230 clocks: 231 minItems: 7 232 maxItems: 7 233 clock-names: 234 items: 235 - const: core 236 description: GPU Core clock 237 - const: iface 238 description: GPU Interface clock 239 - const: mem 240 description: GPU Memory clock 241 - const: mem_iface 242 description: GPU Memory Interface clock 243 - const: alt_mem_iface 244 description: GPU Alternative Memory Interface clock 245 - const: gfx3d 246 description: GPU 3D engine clock 247 - const: rbbmtimer 248 description: GPU RBBM Timer for Adreno 5xx series 249 250 - if: 251 properties: 252 compatible: 253 contains: 254 pattern: '^qcom,adreno-50[56]\.[0-9]+$' 255 then: 256 properties: 257 clocks: 258 minItems: 6 259 maxItems: 6 260 clock-names: 261 items: 262 - const: core 263 description: GPU Core clock 264 - const: iface 265 description: GPU Interface clock 266 - const: mem_iface 267 description: GPU Memory Interface clock 268 - const: alt_mem_iface 269 description: GPU Alternative Memory Interface clock 270 - const: rbbmtimer 271 description: GPU RBBM Timer for Adreno 5xx series 272 - const: alwayson 273 description: GPU AON clock 274 275 - if: 276 properties: 277 compatible: 278 contains: 279 oneOf: 280 - pattern: '^qcom,adreno-508\.[0-9]+$' 281 - pattern: '^qcom,adreno-509\.[0-9]+$' 282 - pattern: '^qcom,adreno-512\.[0-9]+$' 283 - pattern: '^qcom,adreno-540\.[0-9]+$' 284 then: 285 properties: 286 clocks: 287 minItems: 6 288 maxItems: 6 289 clock-names: 290 items: 291 - const: iface 292 description: GPU Interface clock 293 - const: rbbmtimer 294 description: GPU RBBM Timer for Adreno 5xx series 295 - const: mem 296 description: GPU Memory clock 297 - const: mem_iface 298 description: GPU Memory Interface clock 299 - const: rbcpr 300 description: GPU RB Core Power Reduction clock 301 - const: core 302 description: GPU Core clock 303 304 - if: 305 properties: 306 compatible: 307 contains: 308 pattern: '^qcom,adreno-510\.[0-9]+$' 309 then: 310 properties: 311 clocks: 312 minItems: 6 313 maxItems: 6 314 clock-names: 315 items: 316 - const: core 317 description: GPU Core clock 318 - const: iface 319 description: GPU Interface clock 320 - const: mem 321 description: GPU Memory clock 322 - const: mem_iface 323 description: GPU Memory Interface clock 324 - const: rbbmtimer 325 description: GPU RBBM Timer for Adreno 5xx series 326 - const: alwayson 327 description: GPU AON clock 328 329 - if: 330 properties: 331 compatible: 332 contains: 333 pattern: '^qcom,adreno-530\.[0-9]+$' 334 then: 335 properties: 336 clocks: 337 minItems: 5 338 maxItems: 5 339 clock-names: 340 items: 341 - const: core 342 description: GPU Core clock 343 - const: iface 344 description: GPU Interface clock 345 - const: rbbmtimer 346 description: GPU RBBM Timer for Adreno 5xx series 347 - const: mem 348 description: GPU Memory clock 349 - const: mem_iface 350 description: GPU Memory Interface clock 351 352 - if: 353 properties: 354 compatible: 355 contains: 356 enum: 357 - qcom,adreno-610.0 358 - qcom,adreno-619.1 359 - qcom,adreno-07000200 360 then: 361 properties: 362 clocks: 363 minItems: 6 364 maxItems: 6 365 366 clock-names: 367 items: 368 - const: core 369 description: GPU Core clock 370 - const: iface 371 description: GPU Interface clock 372 - const: mem_iface 373 description: GPU Memory Interface clock 374 - const: alt_mem_iface 375 description: GPU Alternative Memory Interface clock 376 - const: gmu 377 description: CX GMU clock 378 - const: xo 379 description: GPUCC clocksource clock 380 381 required: 382 - clocks 383 - clock-names 384 385 - if: 386 properties: 387 compatible: 388 contains: 389 const: qcom,adreno-612.0 390 then: 391 properties: 392 clocks: 393 items: 394 - description: GPU Core clock 395 396 clock-names: 397 items: 398 - const: core 399 400 reg: 401 minItems: 3 402 maxItems: 3 403 404 reg-names: 405 items: 406 - const: kgsl_3d0_reg_memory 407 - const: cx_mem 408 - const: cx_dbgc 409 410 required: 411 - clocks 412 - clock-names 413 414 - if: 415 properties: 416 compatible: 417 contains: 418 enum: 419 - qcom,adreno-44010000 420 - qcom,adreno-44070001 421 then: 422 properties: 423 reg: 424 minItems: 2 425 maxItems: 2 426 427 reg-names: 428 minItems: 2 429 maxItems: 2 430 431 - if: 432 properties: 433 compatible: 434 contains: 435 enum: 436 - qcom,adreno-615.0 437 - qcom,adreno-618.0 438 - qcom,adreno-619.0 439 - qcom,adreno-621.0 440 - qcom,adreno-623.0 441 - qcom,adreno-630.2 442 - qcom,adreno-635.0 443 - qcom,adreno-640.1 444 - qcom,adreno-650.2 445 - qcom,adreno-660.1 446 - qcom,adreno-663.0 447 - qcom,adreno-680.1 448 - qcom,adreno-690.0 449 - qcom,adreno-730.1 450 - qcom,adreno-43030c00 451 - qcom,adreno-43050a01 452 - qcom,adreno-43050c01 453 - qcom,adreno-43051401 454 - qcom,adreno-44010000 455 - qcom,adreno-44070001 456 457 then: # Starting with A6xx, the clocks are usually defined in the GMU node 458 properties: 459 clocks: false 460 clock-names: false 461 462examples: 463 - | 464 465 // Example a3xx/4xx: 466 467 #include <dt-bindings/clock/qcom,mmcc-msm8974.h> 468 #include <dt-bindings/clock/qcom,rpmcc.h> 469 #include <dt-bindings/interrupt-controller/irq.h> 470 #include <dt-bindings/interrupt-controller/arm-gic.h> 471 472 gpu: gpu@fdb00000 { 473 compatible = "qcom,adreno-330.2", "qcom,adreno"; 474 475 reg = <0xfdb00000 0x10000>; 476 reg-names = "kgsl_3d0_reg_memory"; 477 478 clock-names = "core", "iface", "mem_iface"; 479 clocks = <&mmcc OXILI_GFX3D_CLK>, 480 <&mmcc OXILICX_AHB_CLK>, 481 <&mmcc OXILICX_AXI_CLK>; 482 483 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 484 interrupt-names = "kgsl_3d0_irq"; 485 486 sram = <&gpu_sram>; 487 power-domains = <&mmcc OXILICX_GDSC>; 488 operating-points-v2 = <&gpu_opp_table>; 489 iommus = <&gpu_iommu 0>; 490 #cooling-cells = <2>; 491 }; 492 493 ocmem@fdd00000 { 494 compatible = "qcom,msm8974-ocmem"; 495 496 reg = <0xfdd00000 0x2000>, 497 <0xfec00000 0x180000>; 498 reg-names = "ctrl", "mem"; 499 500 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, 501 <&mmcc OCMEMCX_OCMEMNOC_CLK>; 502 clock-names = "core", "iface"; 503 504 #address-cells = <1>; 505 #size-cells = <1>; 506 ranges = <0 0xfec00000 0x100000>; 507 508 gpu_sram: gpu-sram@0 { 509 reg = <0x0 0x100000>; 510 }; 511 }; 512 - | 513 514 // Example a6xx (with GMU): 515 516 #include <dt-bindings/clock/qcom,gpucc-sdm845.h> 517 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 518 #include <dt-bindings/power/qcom-rpmpd.h> 519 #include <dt-bindings/interrupt-controller/irq.h> 520 #include <dt-bindings/interrupt-controller/arm-gic.h> 521 #include <dt-bindings/interconnect/qcom,sdm845.h> 522 523 reserved-memory { 524 #address-cells = <2>; 525 #size-cells = <2>; 526 527 zap_shader_region: gpu@8f200000 { 528 compatible = "shared-dma-pool"; 529 reg = <0x0 0x90b00000 0x0 0xa00000>; 530 no-map; 531 }; 532 }; 533 534 gpu@5000000 { 535 compatible = "qcom,adreno-630.2", "qcom,adreno"; 536 537 reg = <0x5000000 0x40000>, <0x509e000 0x10>; 538 reg-names = "kgsl_3d0_reg_memory", "cx_mem"; 539 540 #cooling-cells = <2>; 541 542 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 543 544 iommus = <&adreno_smmu 0>; 545 546 operating-points-v2 = <&gpu_opp_table>; 547 548 interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>; 549 interconnect-names = "gfx-mem"; 550 551 qcom,gmu = <&gmu>; 552 553 gpu_opp_table: opp-table { 554 compatible = "operating-points-v2"; 555 556 opp-430000000 { 557 opp-hz = /bits/ 64 <430000000>; 558 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 559 opp-peak-kBps = <5412000>; 560 }; 561 562 opp-355000000 { 563 opp-hz = /bits/ 64 <355000000>; 564 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 565 opp-peak-kBps = <3072000>; 566 }; 567 568 opp-267000000 { 569 opp-hz = /bits/ 64 <267000000>; 570 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 571 opp-peak-kBps = <3072000>; 572 }; 573 574 opp-180000000 { 575 opp-hz = /bits/ 64 <180000000>; 576 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 577 opp-peak-kBps = <1804000>; 578 }; 579 }; 580 581 zap-shader { 582 memory-region = <&zap_shader_region>; 583 firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn"; 584 }; 585 }; 586