xref: /linux/Documentation/devicetree/bindings/display/msm/gmu.yaml (revision 7f71507851fc7764b36a3221839607d3a45c2025) 
1# SPDX-License-Identifier: GPL-2.0-only
2# Copyright 2019-2020, The Linux Foundation, All Rights Reserved
3%YAML 1.2
4---
5
6$id: http://devicetree.org/schemas/display/msm/gmu.yaml#
7$schema: http://devicetree.org/meta-schemas/core.yaml#
8
9title: GMU attached to certain Adreno GPUs
10
11maintainers:
12  - Rob Clark <robdclark@gmail.com>
13
14description: |
15  These bindings describe the Graphics Management Unit (GMU) that is attached
16  to members of the Adreno A6xx GPU family. The GMU provides on-device power
17  management and support to improve power efficiency and reduce the load on
18  the CPU.
19
20properties:
21  compatible:
22    oneOf:
23      - items:
24          - pattern: '^qcom,adreno-gmu-[67][0-9][0-9]\.[0-9]$'
25          - const: qcom,adreno-gmu
26      - items:
27          - pattern: '^qcom,adreno-gmu-x[1-9][0-9][0-9]\.[0-9]$'
28          - const: qcom,adreno-gmu
29      - const: qcom,adreno-gmu-wrapper
30
31  reg:
32    minItems: 1
33    maxItems: 4
34
35  reg-names:
36    minItems: 1
37    maxItems: 4
38
39  clocks:
40    minItems: 4
41    maxItems: 7
42
43  clock-names:
44    minItems: 4
45    maxItems: 7
46
47  interrupts:
48    items:
49      - description: GMU HFI interrupt
50      - description: GMU interrupt
51
52  interrupt-names:
53    items:
54      - const: hfi
55      - const: gmu
56
57  power-domains:
58    items:
59      - description: CX power domain
60      - description: GX power domain
61
62  power-domain-names:
63    items:
64      - const: cx
65      - const: gx
66
67  iommus:
68    maxItems: 1
69
70  qcom,qmp:
71    $ref: /schemas/types.yaml#/definitions/phandle
72    description: Reference to the AOSS side-channel message RAM
73
74  operating-points-v2: true
75
76  opp-table:
77    type: object
78
79required:
80  - compatible
81  - reg
82  - reg-names
83  - power-domains
84  - power-domain-names
85
86additionalProperties: false
87
88allOf:
89  - if:
90      properties:
91        compatible:
92          contains:
93            enum:
94              - qcom,adreno-gmu-618.0
95              - qcom,adreno-gmu-630.2
96    then:
97      properties:
98        reg:
99          items:
100            - description: Core GMU registers
101            - description: GMU PDC registers
102            - description: GMU PDC sequence registers
103        reg-names:
104          items:
105            - const: gmu
106            - const: gmu_pdc
107            - const: gmu_pdc_seq
108        clocks:
109          items:
110            - description: GMU clock
111            - description: GPU CX clock
112            - description: GPU AXI clock
113            - description: GPU MEMNOC clock
114        clock-names:
115          items:
116            - const: gmu
117            - const: cxo
118            - const: axi
119            - const: memnoc
120
121  - if:
122      properties:
123        compatible:
124          contains:
125            enum:
126              - qcom,adreno-gmu-635.0
127              - qcom,adreno-gmu-660.1
128              - qcom,adreno-gmu-663.0
129    then:
130      properties:
131        reg:
132          items:
133            - description: Core GMU registers
134            - description: Resource controller registers
135            - description: GMU PDC registers
136        reg-names:
137          items:
138            - const: gmu
139            - const: rscc
140            - const: gmu_pdc
141        clocks:
142          items:
143            - description: GMU clock
144            - description: GPU CX clock
145            - description: GPU AXI clock
146            - description: GPU MEMNOC clock
147            - description: GPU AHB clock
148            - description: GPU HUB CX clock
149            - description: GPU SMMU vote clock
150        clock-names:
151          items:
152            - const: gmu
153            - const: cxo
154            - const: axi
155            - const: memnoc
156            - const: ahb
157            - const: hub
158            - const: smmu_vote
159
160  - if:
161      properties:
162        compatible:
163          contains:
164            enum:
165              - qcom,adreno-gmu-640.1
166    then:
167      properties:
168        reg:
169          items:
170            - description: Core GMU registers
171            - description: GMU PDC registers
172            - description: GMU PDC sequence registers
173        reg-names:
174          items:
175            - const: gmu
176            - const: gmu_pdc
177            - const: gmu_pdc_seq
178
179  - if:
180      properties:
181        compatible:
182          contains:
183            enum:
184              - qcom,adreno-gmu-650.2
185    then:
186      properties:
187        reg:
188          items:
189            - description: Core GMU registers
190            - description: Resource controller registers
191            - description: GMU PDC registers
192            - description: GMU PDC sequence registers
193        reg-names:
194          items:
195            - const: gmu
196            - const: rscc
197            - const: gmu_pdc
198            - const: gmu_pdc_seq
199
200  - if:
201      properties:
202        compatible:
203          contains:
204            enum:
205              - qcom,adreno-gmu-640.1
206              - qcom,adreno-gmu-650.2
207    then:
208      properties:
209        clocks:
210          items:
211            - description: GPU AHB clock
212            - description: GMU clock
213            - description: GPU CX clock
214            - description: GPU AXI clock
215            - description: GPU MEMNOC clock
216        clock-names:
217          items:
218            - const: ahb
219            - const: gmu
220            - const: cxo
221            - const: axi
222            - const: memnoc
223
224  - if:
225      properties:
226        compatible:
227          contains:
228            enum:
229              - qcom,adreno-gmu-730.1
230              - qcom,adreno-gmu-740.1
231              - qcom,adreno-gmu-750.1
232              - qcom,adreno-gmu-x185.1
233    then:
234      properties:
235        reg:
236          items:
237            - description: Core GMU registers
238            - description: Resource controller registers
239            - description: GMU PDC registers
240        reg-names:
241          items:
242            - const: gmu
243            - const: rscc
244            - const: gmu_pdc
245        clocks:
246          items:
247            - description: GPU AHB clock
248            - description: GMU clock
249            - description: GPU CX clock
250            - description: GPU AXI clock
251            - description: GPU MEMNOC clock
252            - description: GMU HUB clock
253            - description: GPUSS DEMET clock
254        clock-names:
255          items:
256            - const: ahb
257            - const: gmu
258            - const: cxo
259            - const: axi
260            - const: memnoc
261            - const: hub
262            - const: demet
263
264      required:
265        - qcom,qmp
266
267  - if:
268      properties:
269        compatible:
270          contains:
271            const: qcom,adreno-gmu-wrapper
272    then:
273      properties:
274        reg:
275          items:
276            - description: GMU wrapper register space
277        reg-names:
278          items:
279            - const: gmu
280    else:
281      required:
282        - clocks
283        - clock-names
284        - interrupts
285        - interrupt-names
286        - iommus
287        - operating-points-v2
288
289examples:
290  - |
291    #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
292    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
293    #include <dt-bindings/interrupt-controller/irq.h>
294    #include <dt-bindings/interrupt-controller/arm-gic.h>
295
296    gmu: gmu@506a000 {
297        compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
298
299        reg = <0x506a000 0x30000>,
300              <0xb280000 0x10000>,
301              <0xb480000 0x10000>;
302        reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
303
304        clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
305                 <&gpucc GPU_CC_CXO_CLK>,
306                 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
307                 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
308        clock-names = "gmu", "cxo", "axi", "memnoc";
309
310        interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
311                     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
312        interrupt-names = "hfi", "gmu";
313
314        power-domains = <&gpucc GPU_CX_GDSC>,
315                        <&gpucc GPU_GX_GDSC>;
316        power-domain-names = "cx", "gx";
317
318        iommus = <&adreno_smmu 5>;
319        operating-points-v2 = <&gmu_opp_table>;
320    };
321
322    gmu_wrapper: gmu@596a000 {
323        compatible = "qcom,adreno-gmu-wrapper";
324        reg = <0x0596a000 0x30000>;
325        reg-names = "gmu";
326        power-domains = <&gpucc GPU_CX_GDSC>,
327                        <&gpucc GPU_GX_GDSC>;
328        power-domain-names = "cx", "gx";
329    };
330