xref: /linux/Documentation/devicetree/bindings/display/msm/gmu.yaml (revision 661fb4e68cf62bf52eacfcd9b3b0d93fe4260c5b) 
1# SPDX-License-Identifier: GPL-2.0-only
2# Copyright 2019-2020, The Linux Foundation, All Rights Reserved
3%YAML 1.2
4---
5
6$id: http://devicetree.org/schemas/display/msm/gmu.yaml#
7$schema: http://devicetree.org/meta-schemas/core.yaml#
8
9title: GMU attached to certain Adreno GPUs
10
11maintainers:
12  - Rob Clark <robdclark@gmail.com>
13
14description: |
15  These bindings describe the Graphics Management Unit (GMU) that is attached
16  to members of the Adreno A6xx GPU family. The GMU provides on-device power
17  management and support to improve power efficiency and reduce the load on
18  the CPU.
19
20properties:
21  compatible:
22    oneOf:
23      - items:
24          - pattern: '^qcom,adreno-gmu-[67][0-9][0-9]\.[0-9]$'
25          - const: qcom,adreno-gmu
26      - items:
27          - pattern: '^qcom,adreno-gmu-x[1-9][0-9][0-9]\.[0-9]$'
28          - const: qcom,adreno-gmu
29      - const: qcom,adreno-gmu-wrapper
30
31  reg:
32    minItems: 1
33    maxItems: 4
34
35  reg-names:
36    minItems: 1
37    maxItems: 4
38
39  clocks:
40    minItems: 4
41    maxItems: 7
42
43  clock-names:
44    minItems: 4
45    maxItems: 7
46
47  interrupts:
48    items:
49      - description: GMU HFI interrupt
50      - description: GMU interrupt
51
52  interrupt-names:
53    items:
54      - const: hfi
55      - const: gmu
56
57  power-domains:
58    items:
59      - description: CX power domain
60      - description: GX power domain
61
62  power-domain-names:
63    items:
64      - const: cx
65      - const: gx
66
67  iommus:
68    maxItems: 1
69
70  qcom,qmp:
71    $ref: /schemas/types.yaml#/definitions/phandle
72    description: Reference to the AOSS side-channel message RAM
73
74  operating-points-v2: true
75
76  opp-table:
77    type: object
78
79required:
80  - compatible
81  - reg
82  - reg-names
83  - power-domains
84  - power-domain-names
85
86additionalProperties: false
87
88allOf:
89  - if:
90      properties:
91        compatible:
92          contains:
93            enum:
94              - qcom,adreno-gmu-618.0
95              - qcom,adreno-gmu-630.2
96    then:
97      properties:
98        reg:
99          items:
100            - description: Core GMU registers
101            - description: GMU PDC registers
102            - description: GMU PDC sequence registers
103        reg-names:
104          items:
105            - const: gmu
106            - const: gmu_pdc
107            - const: gmu_pdc_seq
108        clocks:
109          items:
110            - description: GMU clock
111            - description: GPU CX clock
112            - description: GPU AXI clock
113            - description: GPU MEMNOC clock
114        clock-names:
115          items:
116            - const: gmu
117            - const: cxo
118            - const: axi
119            - const: memnoc
120
121  - if:
122      properties:
123        compatible:
124          contains:
125            enum:
126              - qcom,adreno-gmu-635.0
127              - qcom,adreno-gmu-660.1
128    then:
129      properties:
130        reg:
131          items:
132            - description: Core GMU registers
133            - description: Resource controller registers
134            - description: GMU PDC registers
135        reg-names:
136          items:
137            - const: gmu
138            - const: rscc
139            - const: gmu_pdc
140        clocks:
141          items:
142            - description: GMU clock
143            - description: GPU CX clock
144            - description: GPU AXI clock
145            - description: GPU MEMNOC clock
146            - description: GPU AHB clock
147            - description: GPU HUB CX clock
148            - description: GPU SMMU vote clock
149        clock-names:
150          items:
151            - const: gmu
152            - const: cxo
153            - const: axi
154            - const: memnoc
155            - const: ahb
156            - const: hub
157            - const: smmu_vote
158
159  - if:
160      properties:
161        compatible:
162          contains:
163            enum:
164              - qcom,adreno-gmu-640.1
165    then:
166      properties:
167        reg:
168          items:
169            - description: Core GMU registers
170            - description: GMU PDC registers
171            - description: GMU PDC sequence registers
172        reg-names:
173          items:
174            - const: gmu
175            - const: gmu_pdc
176            - const: gmu_pdc_seq
177
178  - if:
179      properties:
180        compatible:
181          contains:
182            enum:
183              - qcom,adreno-gmu-650.2
184    then:
185      properties:
186        reg:
187          items:
188            - description: Core GMU registers
189            - description: Resource controller registers
190            - description: GMU PDC registers
191            - description: GMU PDC sequence registers
192        reg-names:
193          items:
194            - const: gmu
195            - const: rscc
196            - const: gmu_pdc
197            - const: gmu_pdc_seq
198
199  - if:
200      properties:
201        compatible:
202          contains:
203            enum:
204              - qcom,adreno-gmu-640.1
205              - qcom,adreno-gmu-650.2
206    then:
207      properties:
208        clocks:
209          items:
210            - description: GPU AHB clock
211            - description: GMU clock
212            - description: GPU CX clock
213            - description: GPU AXI clock
214            - description: GPU MEMNOC clock
215        clock-names:
216          items:
217            - const: ahb
218            - const: gmu
219            - const: cxo
220            - const: axi
221            - const: memnoc
222
223  - if:
224      properties:
225        compatible:
226          contains:
227            enum:
228              - qcom,adreno-gmu-730.1
229              - qcom,adreno-gmu-740.1
230              - qcom,adreno-gmu-750.1
231              - qcom,adreno-gmu-x185.1
232    then:
233      properties:
234        reg:
235          items:
236            - description: Core GMU registers
237            - description: Resource controller registers
238            - description: GMU PDC registers
239        reg-names:
240          items:
241            - const: gmu
242            - const: rscc
243            - const: gmu_pdc
244        clocks:
245          items:
246            - description: GPU AHB clock
247            - description: GMU clock
248            - description: GPU CX clock
249            - description: GPU AXI clock
250            - description: GPU MEMNOC clock
251            - description: GMU HUB clock
252            - description: GPUSS DEMET clock
253        clock-names:
254          items:
255            - const: ahb
256            - const: gmu
257            - const: cxo
258            - const: axi
259            - const: memnoc
260            - const: hub
261            - const: demet
262
263      required:
264        - qcom,qmp
265
266  - if:
267      properties:
268        compatible:
269          contains:
270            const: qcom,adreno-gmu-wrapper
271    then:
272      properties:
273        reg:
274          items:
275            - description: GMU wrapper register space
276        reg-names:
277          items:
278            - const: gmu
279    else:
280      required:
281        - clocks
282        - clock-names
283        - interrupts
284        - interrupt-names
285        - iommus
286        - operating-points-v2
287
288examples:
289  - |
290    #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
291    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
292    #include <dt-bindings/interrupt-controller/irq.h>
293    #include <dt-bindings/interrupt-controller/arm-gic.h>
294
295    gmu: gmu@506a000 {
296        compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
297
298        reg = <0x506a000 0x30000>,
299              <0xb280000 0x10000>,
300              <0xb480000 0x10000>;
301        reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
302
303        clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
304                 <&gpucc GPU_CC_CXO_CLK>,
305                 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
306                 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
307        clock-names = "gmu", "cxo", "axi", "memnoc";
308
309        interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
310                     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
311        interrupt-names = "hfi", "gmu";
312
313        power-domains = <&gpucc GPU_CX_GDSC>,
314                        <&gpucc GPU_GX_GDSC>;
315        power-domain-names = "cx", "gx";
316
317        iommus = <&adreno_smmu 5>;
318        operating-points-v2 = <&gmu_opp_table>;
319    };
320
321    gmu_wrapper: gmu@596a000 {
322        compatible = "qcom,adreno-gmu-wrapper";
323        reg = <0x0596a000 0x30000>;
324        reg-names = "gmu";
325        power-domains = <&gpucc GPU_CX_GDSC>,
326                        <&gpucc GPU_GX_GDSC>;
327        power-domain-names = "cx", "gx";
328    };
329