xref: /linux/Documentation/devicetree/bindings/display/msm/gmu.yaml (revision 55a42f78ffd386e01a5404419f8c5ded7db70a21) 
1# SPDX-License-Identifier: GPL-2.0-only
2# Copyright 2019-2020, The Linux Foundation, All Rights Reserved
3%YAML 1.2
4---
5
6$id: http://devicetree.org/schemas/display/msm/gmu.yaml#
7$schema: http://devicetree.org/meta-schemas/core.yaml#
8
9title: GMU attached to certain Adreno GPUs
10
11maintainers:
12  - Rob Clark <robdclark@gmail.com>
13
14description: |
15  These bindings describe the Graphics Management Unit (GMU) that is attached
16  to members of the Adreno A6xx GPU family. The GMU provides on-device power
17  management and support to improve power efficiency and reduce the load on
18  the CPU.
19
20properties:
21  compatible:
22    oneOf:
23      - items:
24          - pattern: '^qcom,adreno-gmu-[67][0-9][0-9]\.[0-9]$'
25          - const: qcom,adreno-gmu
26      - items:
27          - pattern: '^qcom,adreno-gmu-x[1-9][0-9][0-9]\.[0-9]$'
28          - const: qcom,adreno-gmu
29      - const: qcom,adreno-gmu-wrapper
30
31  reg:
32    minItems: 1
33    maxItems: 4
34
35  reg-names:
36    minItems: 1
37    maxItems: 4
38
39  clocks:
40    minItems: 4
41    maxItems: 7
42
43  clock-names:
44    minItems: 4
45    maxItems: 7
46
47  interrupts:
48    items:
49      - description: GMU HFI interrupt
50      - description: GMU interrupt
51
52  interrupt-names:
53    items:
54      - const: hfi
55      - const: gmu
56
57  power-domains:
58    items:
59      - description: CX power domain
60      - description: GX power domain
61
62  power-domain-names:
63    items:
64      - const: cx
65      - const: gx
66
67  iommus:
68    maxItems: 1
69
70  qcom,qmp:
71    $ref: /schemas/types.yaml#/definitions/phandle
72    description: Reference to the AOSS side-channel message RAM
73
74  operating-points-v2: true
75
76  opp-table:
77    type: object
78
79required:
80  - compatible
81  - reg
82  - reg-names
83  - power-domains
84  - power-domain-names
85
86additionalProperties: false
87
88allOf:
89  - if:
90      properties:
91        compatible:
92          contains:
93            enum:
94              - qcom,adreno-gmu-618.0
95              - qcom,adreno-gmu-630.2
96    then:
97      properties:
98        reg:
99          items:
100            - description: Core GMU registers
101            - description: GMU PDC registers
102            - description: GMU PDC sequence registers
103        reg-names:
104          items:
105            - const: gmu
106            - const: gmu_pdc
107            - const: gmu_pdc_seq
108        clocks:
109          items:
110            - description: GMU clock
111            - description: GPU CX clock
112            - description: GPU AXI clock
113            - description: GPU MEMNOC clock
114        clock-names:
115          items:
116            - const: gmu
117            - const: cxo
118            - const: axi
119            - const: memnoc
120
121  - if:
122      properties:
123        compatible:
124          contains:
125            enum:
126              - qcom,adreno-gmu-623.0
127    then:
128      properties:
129        reg:
130          items:
131            - description: Core GMU registers
132            - description: Resource controller registers
133            - description: GMU PDC registers
134        reg-names:
135          items:
136            - const: gmu
137            - const: rscc
138            - const: gmu_pdc
139        clocks:
140          items:
141            - description: GMU clock
142            - description: GPU CX clock
143            - description: GPU AXI clock
144            - description: GPU MEMNOC clock
145            - description: GPU AHB clock
146            - description: GPU HUB CX clock
147        clock-names:
148          items:
149            - const: gmu
150            - const: cxo
151            - const: axi
152            - const: memnoc
153            - const: ahb
154            - const: hub
155
156  - if:
157      properties:
158        compatible:
159          contains:
160            enum:
161              - qcom,adreno-gmu-635.0
162              - qcom,adreno-gmu-660.1
163              - qcom,adreno-gmu-663.0
164    then:
165      properties:
166        reg:
167          items:
168            - description: Core GMU registers
169            - description: Resource controller registers
170            - description: GMU PDC registers
171        reg-names:
172          items:
173            - const: gmu
174            - const: rscc
175            - const: gmu_pdc
176        clocks:
177          items:
178            - description: GMU clock
179            - description: GPU CX clock
180            - description: GPU AXI clock
181            - description: GPU MEMNOC clock
182            - description: GPU AHB clock
183            - description: GPU HUB CX clock
184            - description: GPU SMMU vote clock
185        clock-names:
186          items:
187            - const: gmu
188            - const: cxo
189            - const: axi
190            - const: memnoc
191            - const: ahb
192            - const: hub
193            - const: smmu_vote
194
195  - if:
196      properties:
197        compatible:
198          contains:
199            enum:
200              - qcom,adreno-gmu-640.1
201    then:
202      properties:
203        reg:
204          items:
205            - description: Core GMU registers
206            - description: GMU PDC registers
207            - description: GMU PDC sequence registers
208        reg-names:
209          items:
210            - const: gmu
211            - const: gmu_pdc
212            - const: gmu_pdc_seq
213
214  - if:
215      properties:
216        compatible:
217          contains:
218            enum:
219              - qcom,adreno-gmu-650.2
220    then:
221      properties:
222        reg:
223          items:
224            - description: Core GMU registers
225            - description: Resource controller registers
226            - description: GMU PDC registers
227            - description: GMU PDC sequence registers
228        reg-names:
229          items:
230            - const: gmu
231            - const: rscc
232            - const: gmu_pdc
233            - const: gmu_pdc_seq
234
235  - if:
236      properties:
237        compatible:
238          contains:
239            enum:
240              - qcom,adreno-gmu-640.1
241              - qcom,adreno-gmu-650.2
242    then:
243      properties:
244        clocks:
245          items:
246            - description: GPU AHB clock
247            - description: GMU clock
248            - description: GPU CX clock
249            - description: GPU AXI clock
250            - description: GPU MEMNOC clock
251        clock-names:
252          items:
253            - const: ahb
254            - const: gmu
255            - const: cxo
256            - const: axi
257            - const: memnoc
258
259  - if:
260      properties:
261        compatible:
262          contains:
263            enum:
264              - qcom,adreno-gmu-730.1
265              - qcom,adreno-gmu-740.1
266              - qcom,adreno-gmu-750.1
267              - qcom,adreno-gmu-x185.1
268    then:
269      properties:
270        reg:
271          items:
272            - description: Core GMU registers
273            - description: Resource controller registers
274            - description: GMU PDC registers
275        reg-names:
276          items:
277            - const: gmu
278            - const: rscc
279            - const: gmu_pdc
280        clocks:
281          items:
282            - description: GPU AHB clock
283            - description: GMU clock
284            - description: GPU CX clock
285            - description: GPU AXI clock
286            - description: GPU MEMNOC clock
287            - description: GMU HUB clock
288            - description: GPUSS DEMET clock
289        clock-names:
290          items:
291            - const: ahb
292            - const: gmu
293            - const: cxo
294            - const: axi
295            - const: memnoc
296            - const: hub
297            - const: demet
298
299      required:
300        - qcom,qmp
301
302  - if:
303      properties:
304        compatible:
305          contains:
306            const: qcom,adreno-gmu-wrapper
307    then:
308      properties:
309        reg:
310          items:
311            - description: GMU wrapper register space
312        reg-names:
313          items:
314            - const: gmu
315    else:
316      required:
317        - clocks
318        - clock-names
319        - interrupts
320        - interrupt-names
321        - iommus
322        - operating-points-v2
323
324examples:
325  - |
326    #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
327    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
328    #include <dt-bindings/interrupt-controller/irq.h>
329    #include <dt-bindings/interrupt-controller/arm-gic.h>
330
331    gmu: gmu@506a000 {
332        compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
333
334        reg = <0x506a000 0x30000>,
335              <0xb280000 0x10000>,
336              <0xb480000 0x10000>;
337        reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
338
339        clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
340                 <&gpucc GPU_CC_CXO_CLK>,
341                 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
342                 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
343        clock-names = "gmu", "cxo", "axi", "memnoc";
344
345        interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
346                     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
347        interrupt-names = "hfi", "gmu";
348
349        power-domains = <&gpucc GPU_CX_GDSC>,
350                        <&gpucc GPU_GX_GDSC>;
351        power-domain-names = "cx", "gx";
352
353        iommus = <&adreno_smmu 5>;
354        operating-points-v2 = <&gmu_opp_table>;
355    };
356
357    gmu_wrapper: gmu@596a000 {
358        compatible = "qcom,adreno-gmu-wrapper";
359        reg = <0x0596a000 0x30000>;
360        reg-names = "gmu";
361        power-domains = <&gpucc GPU_CX_GDSC>,
362                        <&gpucc GPU_GX_GDSC>;
363        power-domain-names = "cx", "gx";
364    };
365