xref: /linux/Documentation/devicetree/bindings/display/msm/gmu.yaml (revision 3a2c4d55e32ad65efebdb6de44eef3bfa08bb49d) 
1# SPDX-License-Identifier: GPL-2.0-only
2# Copyright 2019-2020, The Linux Foundation, All Rights Reserved
3%YAML 1.2
4---
5
6$id: http://devicetree.org/schemas/display/msm/gmu.yaml#
7$schema: http://devicetree.org/meta-schemas/core.yaml#
8
9title: GMU attached to certain Adreno GPUs
10
11maintainers:
12  - Rob Clark <robdclark@gmail.com>
13
14description: |
15  These bindings describe the Graphics Management Unit (GMU) that is attached
16  to members of the Adreno A6xx GPU family. The GMU provides on-device power
17  management and support to improve power efficiency and reduce the load on
18  the CPU.
19
20properties:
21  compatible:
22    oneOf:
23      - items:
24          - pattern: '^qcom,adreno-gmu-[6-8][0-9][0-9]\.[0-9]$'
25          - const: qcom,adreno-gmu
26      - items:
27          - pattern: '^qcom,adreno-gmu-x[1-9][0-9][0-9]\.[0-9]$'
28          - const: qcom,adreno-gmu
29      - const: qcom,adreno-gmu-wrapper
30
31  reg:
32    minItems: 1
33    maxItems: 4
34
35  reg-names:
36    minItems: 1
37    maxItems: 4
38
39  clocks:
40    minItems: 4
41    maxItems: 7
42
43  clock-names:
44    minItems: 4
45    maxItems: 7
46
47  interrupts:
48    items:
49      - description: GMU HFI interrupt
50      - description: GMU interrupt
51
52  interrupt-names:
53    items:
54      - const: hfi
55      - const: gmu
56
57  power-domains:
58    items:
59      - description: CX power domain
60      - description: GX power domain
61
62  power-domain-names:
63    items:
64      - const: cx
65      - const: gx
66
67  iommus:
68    maxItems: 1
69
70  qcom,qmp:
71    $ref: /schemas/types.yaml#/definitions/phandle
72    description: Reference to the AOSS side-channel message RAM
73
74  operating-points-v2: true
75
76  opp-table:
77    type: object
78
79required:
80  - compatible
81  - reg
82  - reg-names
83  - power-domains
84  - power-domain-names
85
86additionalProperties: false
87
88allOf:
89  - if:
90      properties:
91        compatible:
92          contains:
93            enum:
94              - qcom,adreno-gmu-615.0
95              - qcom,adreno-gmu-618.0
96              - qcom,adreno-gmu-630.2
97    then:
98      properties:
99        reg:
100          items:
101            - description: Core GMU registers
102            - description: GMU PDC registers
103            - description: GMU PDC sequence registers
104        reg-names:
105          items:
106            - const: gmu
107            - const: gmu_pdc
108            - const: gmu_pdc_seq
109        clocks:
110          items:
111            - description: GMU clock
112            - description: GPU CX clock
113            - description: GPU AXI clock
114            - description: GPU MEMNOC clock
115        clock-names:
116          items:
117            - const: gmu
118            - const: cxo
119            - const: axi
120            - const: memnoc
121
122  - if:
123      properties:
124        compatible:
125          contains:
126            enum:
127              - qcom,adreno-gmu-623.0
128    then:
129      properties:
130        reg:
131          items:
132            - description: Core GMU registers
133            - description: Resource controller registers
134            - description: GMU PDC registers
135        reg-names:
136          items:
137            - const: gmu
138            - const: rscc
139            - const: gmu_pdc
140        clocks:
141          items:
142            - description: GMU clock
143            - description: GPU CX clock
144            - description: GPU AXI clock
145            - description: GPU MEMNOC clock
146            - description: GPU AHB clock
147            - description: GPU HUB CX clock
148        clock-names:
149          items:
150            - const: gmu
151            - const: cxo
152            - const: axi
153            - const: memnoc
154            - const: ahb
155            - const: hub
156
157  - if:
158      properties:
159        compatible:
160          contains:
161            enum:
162              - qcom,adreno-gmu-635.0
163              - qcom,adreno-gmu-660.1
164              - qcom,adreno-gmu-663.0
165    then:
166      properties:
167        reg:
168          items:
169            - description: Core GMU registers
170            - description: Resource controller registers
171            - description: GMU PDC registers
172        reg-names:
173          items:
174            - const: gmu
175            - const: rscc
176            - const: gmu_pdc
177        clocks:
178          items:
179            - description: GMU clock
180            - description: GPU CX clock
181            - description: GPU AXI clock
182            - description: GPU MEMNOC clock
183            - description: GPU AHB clock
184            - description: GPU HUB CX clock
185            - description: GPU SMMU vote clock
186        clock-names:
187          items:
188            - const: gmu
189            - const: cxo
190            - const: axi
191            - const: memnoc
192            - const: ahb
193            - const: hub
194            - const: smmu_vote
195
196  - if:
197      properties:
198        compatible:
199          contains:
200            enum:
201              - qcom,adreno-gmu-640.1
202    then:
203      properties:
204        reg:
205          items:
206            - description: Core GMU registers
207            - description: GMU PDC registers
208            - description: GMU PDC sequence registers
209        reg-names:
210          items:
211            - const: gmu
212            - const: gmu_pdc
213            - const: gmu_pdc_seq
214
215  - if:
216      properties:
217        compatible:
218          contains:
219            enum:
220              - qcom,adreno-gmu-650.2
221    then:
222      properties:
223        reg:
224          items:
225            - description: Core GMU registers
226            - description: Resource controller registers
227            - description: GMU PDC registers
228            - description: GMU PDC sequence registers
229        reg-names:
230          items:
231            - const: gmu
232            - const: rscc
233            - const: gmu_pdc
234            - const: gmu_pdc_seq
235
236  - if:
237      properties:
238        compatible:
239          contains:
240            enum:
241              - qcom,adreno-gmu-640.1
242              - qcom,adreno-gmu-650.2
243    then:
244      properties:
245        clocks:
246          items:
247            - description: GPU AHB clock
248            - description: GMU clock
249            - description: GPU CX clock
250            - description: GPU AXI clock
251            - description: GPU MEMNOC clock
252        clock-names:
253          items:
254            - const: ahb
255            - const: gmu
256            - const: cxo
257            - const: axi
258            - const: memnoc
259
260  - if:
261      properties:
262        compatible:
263          contains:
264            enum:
265              - qcom,adreno-gmu-722.0
266              - qcom,adreno-gmu-730.1
267              - qcom,adreno-gmu-740.1
268              - qcom,adreno-gmu-750.1
269              - qcom,adreno-gmu-x185.1
270    then:
271      properties:
272        reg:
273          items:
274            - description: Core GMU registers
275            - description: Resource controller registers
276            - description: GMU PDC registers
277        reg-names:
278          items:
279            - const: gmu
280            - const: rscc
281            - const: gmu_pdc
282        clocks:
283          items:
284            - description: GPU AHB clock
285            - description: GMU clock
286            - description: GPU CX clock
287            - description: GPU AXI clock
288            - description: GPU MEMNOC clock
289            - description: GMU HUB clock
290            - description: GPUSS DEMET clock
291        clock-names:
292          items:
293            - const: ahb
294            - const: gmu
295            - const: cxo
296            - const: axi
297            - const: memnoc
298            - const: hub
299            - const: demet
300
301      required:
302        - qcom,qmp
303
304  - if:
305      properties:
306        compatible:
307          contains:
308            const: qcom,adreno-gmu-810.0
309    then:
310      properties:
311        reg:
312          items:
313            - description: Core GMU registers
314        reg-names:
315          items:
316            - const: gmu
317        clocks:
318          items:
319            - description: GPU AHB clock
320            - description: GMU clock
321            - description: GPU CX clock
322            - description: GPU AXI clock
323            - description: GPU MEMNOC clock
324            - description: GMU HUB clock
325        clock-names:
326          items:
327            - const: ahb
328            - const: gmu
329            - const: cxo
330            - const: axi
331            - const: memnoc
332            - const: hub
333
334  - if:
335      properties:
336        compatible:
337          contains:
338            const: qcom,adreno-gmu-840.1
339    then:
340      properties:
341        reg:
342          items:
343            - description: Core GMU registers
344        reg-names:
345          items:
346            - const: gmu
347        clocks:
348          items:
349            - description: GPU AHB clock
350            - description: GMU clock
351            - description: GPU CX clock
352            - description: GPU MEMNOC clock
353            - description: GMU HUB clock
354        clock-names:
355          items:
356            - const: ahb
357            - const: gmu
358            - const: cxo
359            - const: memnoc
360            - const: hub
361
362  - if:
363      properties:
364        compatible:
365          contains:
366            const: qcom,adreno-gmu-x285.1
367    then:
368      properties:
369        reg:
370          items:
371            - description: Core GMU registers
372        reg-names:
373          items:
374            - const: gmu
375        clocks:
376          items:
377            - description: GPU AHB clock
378            - description: GMU clock
379            - description: GPU CX clock
380            - description: GPU MEMNOC clock
381            - description: GMU HUB clock
382            - description: GMU RSCC HUB clock
383        clock-names:
384          items:
385            - const: ahb
386            - const: gmu
387            - const: cxo
388            - const: memnoc
389            - const: hub
390            - const: rscc
391
392  - if:
393      properties:
394        compatible:
395          contains:
396            const: qcom,adreno-gmu-wrapper
397    then:
398      properties:
399        reg:
400          items:
401            - description: GMU wrapper register space
402        reg-names:
403          items:
404            - const: gmu
405    else:
406      required:
407        - clocks
408        - clock-names
409        - interrupts
410        - interrupt-names
411        - iommus
412        - operating-points-v2
413
414examples:
415  - |
416    #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
417    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
418    #include <dt-bindings/interrupt-controller/irq.h>
419    #include <dt-bindings/interrupt-controller/arm-gic.h>
420
421    gmu: gmu@506a000 {
422        compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
423
424        reg = <0x506a000 0x30000>,
425              <0xb280000 0x10000>,
426              <0xb480000 0x10000>;
427        reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
428
429        clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
430                 <&gpucc GPU_CC_CXO_CLK>,
431                 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
432                 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
433        clock-names = "gmu", "cxo", "axi", "memnoc";
434
435        interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
436                     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
437        interrupt-names = "hfi", "gmu";
438
439        power-domains = <&gpucc GPU_CX_GDSC>,
440                        <&gpucc GPU_GX_GDSC>;
441        power-domain-names = "cx", "gx";
442
443        iommus = <&adreno_smmu 5>;
444        operating-points-v2 = <&gmu_opp_table>;
445    };
446
447    gmu_wrapper: gmu@596a000 {
448        compatible = "qcom,adreno-gmu-wrapper";
449        reg = <0x0596a000 0x30000>;
450        reg-names = "gmu";
451        power-domains = <&gpucc GPU_CX_GDSC>,
452                        <&gpucc GPU_GX_GDSC>;
453        power-domain-names = "cx", "gx";
454    };
455