1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/msm/dsi-phy-7nm.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Display DSI 7nm PHY 8 9maintainers: 10 - Jonathan Marek <jonathan@marek.ca> 11 12allOf: 13 - $ref: dsi-phy-common.yaml# 14 15properties: 16 compatible: 17 enum: 18 - qcom,dsi-phy-7nm 19 - qcom,dsi-phy-7nm-8150 20 - qcom,sa8775p-dsi-phy-5nm 21 - qcom,sar2130p-dsi-phy-5nm 22 - qcom,sc7280-dsi-phy-7nm 23 - qcom,sm6375-dsi-phy-7nm 24 - qcom,sm8350-dsi-phy-5nm 25 - qcom,sm8450-dsi-phy-5nm 26 - qcom,sm8550-dsi-phy-4nm 27 - qcom,sm8650-dsi-phy-4nm 28 29 reg: 30 items: 31 - description: dsi phy register set 32 - description: dsi phy lane register set 33 - description: dsi pll register set 34 35 reg-names: 36 items: 37 - const: dsi_phy 38 - const: dsi_phy_lane 39 - const: dsi_pll 40 41 vdds-supply: 42 description: | 43 Connected to VDD_A_DSI_PLL_0P9 pin (or VDDA_DSI{0,1}_PLL_0P9 for sm8150) 44 45 phy-type: 46 description: D-PHY (default) or C-PHY mode 47 enum: [ 10, 11 ] 48 default: 10 49 50required: 51 - compatible 52 - reg 53 - reg-names 54 55unevaluatedProperties: false 56 57examples: 58 - | 59 #include <dt-bindings/clock/qcom,dispcc-sm8250.h> 60 #include <dt-bindings/clock/qcom,rpmh.h> 61 62 dsi-phy@ae94400 { 63 compatible = "qcom,dsi-phy-7nm"; 64 reg = <0x0ae94400 0x200>, 65 <0x0ae94600 0x280>, 66 <0x0ae94900 0x260>; 67 reg-names = "dsi_phy", 68 "dsi_phy_lane", 69 "dsi_pll"; 70 71 #clock-cells = <1>; 72 #phy-cells = <0>; 73 74 vdds-supply = <&vreg_l5a_0p88>; 75 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 76 <&rpmhcc RPMH_CXO_CLK>; 77 clock-names = "iface", "ref"; 78 }; 79