xref: /linux/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml (revision beaea9c4ba2d8ef1b10223dc3a75a7d7be3e5cd9) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dsi-phy-7nm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display DSI 7nm PHY
8
9maintainers:
10  - Jonathan Marek <jonathan@marek.ca>
11
12allOf:
13  - $ref: dsi-phy-common.yaml#
14
15properties:
16  compatible:
17    enum:
18      - qcom,dsi-phy-7nm
19      - qcom,dsi-phy-7nm-8150
20      - qcom,sa8775p-dsi-phy-5nm
21      - qcom,sar2130p-dsi-phy-5nm
22      - qcom,sc7280-dsi-phy-7nm
23      - qcom,sm6375-dsi-phy-7nm
24      - qcom,sm8350-dsi-phy-5nm
25      - qcom,sm8450-dsi-phy-5nm
26      - qcom,sm8550-dsi-phy-4nm
27      - qcom,sm8650-dsi-phy-4nm
28      - qcom,sm8750-dsi-phy-3nm
29
30  reg:
31    items:
32      - description: dsi phy register set
33      - description: dsi phy lane register set
34      - description: dsi pll register set
35
36  reg-names:
37    items:
38      - const: dsi_phy
39      - const: dsi_phy_lane
40      - const: dsi_pll
41
42  vdds-supply:
43    description: |
44      Connected to VDD_A_DSI_PLL_0P9 pin (or VDDA_DSI{0,1}_PLL_0P9 for sm8150)
45
46  phy-type:
47    description: D-PHY (default) or C-PHY mode
48    enum: [ 10, 11 ]
49    default: 10
50
51required:
52  - compatible
53  - reg
54  - reg-names
55
56unevaluatedProperties: false
57
58examples:
59  - |
60    #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
61    #include <dt-bindings/clock/qcom,rpmh.h>
62
63    dsi-phy@ae94400 {
64        compatible = "qcom,dsi-phy-7nm";
65        reg = <0x0ae94400 0x200>,
66              <0x0ae94600 0x280>,
67              <0x0ae94900 0x260>;
68        reg-names = "dsi_phy",
69                    "dsi_phy_lane",
70                    "dsi_pll";
71
72        #clock-cells = <1>;
73        #phy-cells = <0>;
74
75        vdds-supply = <&vreg_l5a_0p88>;
76        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
77                 <&rpmhcc RPMH_CXO_CLK>;
78        clock-names = "iface", "ref";
79    };
80