xref: /linux/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml (revision ae22a94997b8a03dcb3c922857c203246711f9d4) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dsi-phy-28nm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display DSI 28nm PHY
8
9maintainers:
10  - Krishna Manikandan <quic_mkrishn@quicinc.com>
11
12allOf:
13  - $ref: dsi-phy-common.yaml#
14
15properties:
16  compatible:
17    enum:
18      - qcom,dsi-phy-28nm-8226
19      - qcom,dsi-phy-28nm-8960
20      - qcom,dsi-phy-28nm-hpm
21      - qcom,dsi-phy-28nm-hpm-fam-b
22      - qcom,dsi-phy-28nm-lp
23
24  reg:
25    items:
26      - description: dsi pll register set
27      - description: dsi phy register set
28      - description: dsi phy regulator register set
29
30  reg-names:
31    items:
32      - const: dsi_pll
33      - const: dsi_phy
34      - const: dsi_phy_regulator
35
36  vddio-supply:
37    description: Phandle to vdd-io regulator device node.
38
39  qcom,dsi-phy-regulator-ldo-mode:
40    type: boolean
41    description: Indicates if the LDO mode PHY regulator is wanted.
42
43required:
44  - compatible
45  - reg
46  - reg-names
47  - vddio-supply
48
49unevaluatedProperties: false
50
51examples:
52  - |
53     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
54     #include <dt-bindings/clock/qcom,rpmh.h>
55
56     dsi-phy@fd922a00 {
57         compatible = "qcom,dsi-phy-28nm-lp";
58         reg = <0xfd922a00 0xd4>,
59               <0xfd922b00 0x2b0>,
60               <0xfd922d80 0x7b>;
61         reg-names = "dsi_pll",
62                     "dsi_phy",
63                     "dsi_phy_regulator";
64
65         #clock-cells = <1>;
66         #phy-cells = <0>;
67
68         vddio-supply = <&vddio_reg>;
69
70         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
71                  <&rpmhcc RPMH_CXO_CLK>;
72         clock-names = "iface", "ref";
73     };
74...
75