xref: /linux/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml (revision 34dc1baba215b826e454b8d19e4f24adbeb7d00d) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dsi-phy-14nm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display DSI 14nm PHY
8
9maintainers:
10  - Krishna Manikandan <quic_mkrishn@quicinc.com>
11
12allOf:
13  - $ref: dsi-phy-common.yaml#
14
15properties:
16  compatible:
17    enum:
18      - qcom,dsi-phy-14nm
19      - qcom,dsi-phy-14nm-2290
20      - qcom,dsi-phy-14nm-660
21      - qcom,dsi-phy-14nm-8953
22      - qcom,sm6125-dsi-phy-14nm
23
24  reg:
25    items:
26      - description: dsi phy register set
27      - description: dsi phy lane register set
28      - description: dsi pll register set
29
30  reg-names:
31    items:
32      - const: dsi_phy
33      - const: dsi_phy_lane
34      - const: dsi_pll
35
36  vcca-supply:
37    description: Phandle to vcca regulator device node.
38
39  power-domains:
40    description:
41      A phandle and PM domain specifier for an optional power domain.
42    maxItems: 1
43
44  required-opps:
45    description:
46      A phandle to an OPP node describing the power domain's performance point.
47    maxItems: 1
48
49required:
50  - compatible
51  - reg
52  - reg-names
53
54unevaluatedProperties: false
55
56examples:
57  - |
58     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
59     #include <dt-bindings/clock/qcom,rpmh.h>
60
61     dsi-phy@ae94400 {
62         compatible = "qcom,dsi-phy-14nm";
63         reg = <0x0ae94400 0x200>,
64               <0x0ae94600 0x280>,
65               <0x0ae94a00 0x1e0>;
66         reg-names = "dsi_phy",
67                     "dsi_phy_lane",
68                     "dsi_pll";
69
70         #clock-cells = <1>;
71         #phy-cells = <0>;
72
73         vcca-supply = <&vcca_reg>;
74         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
75                  <&rpmhcc RPMH_CXO_CLK>;
76         clock-names = "iface", "ref";
77     };
78...
79