1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Display DSI controller 8 9maintainers: 10 - Krishna Manikandan <quic_mkrishn@quicinc.com> 11 12properties: 13 compatible: 14 oneOf: 15 - items: 16 - enum: 17 - qcom,apq8064-dsi-ctrl 18 - qcom,kaanapali-dsi-ctrl 19 - qcom,msm8226-dsi-ctrl 20 - qcom,msm8916-dsi-ctrl 21 - qcom,msm8953-dsi-ctrl 22 - qcom,msm8974-dsi-ctrl 23 - qcom,msm8976-dsi-ctrl 24 - qcom,msm8996-dsi-ctrl 25 - qcom,msm8998-dsi-ctrl 26 - qcom,qcm2290-dsi-ctrl 27 - qcom,sa8775p-dsi-ctrl 28 - qcom,sar2130p-dsi-ctrl 29 - qcom,sc7180-dsi-ctrl 30 - qcom,sc7280-dsi-ctrl 31 - qcom,sc8180x-dsi-ctrl 32 - qcom,sdm660-dsi-ctrl 33 - qcom,sdm670-dsi-ctrl 34 - qcom,sdm845-dsi-ctrl 35 - qcom,sm6115-dsi-ctrl 36 - qcom,sm6125-dsi-ctrl 37 - qcom,sm6150-dsi-ctrl 38 - qcom,sm6350-dsi-ctrl 39 - qcom,sm6375-dsi-ctrl 40 - qcom,sm7150-dsi-ctrl 41 - qcom,sm8150-dsi-ctrl 42 - qcom,sm8250-dsi-ctrl 43 - qcom,sm8350-dsi-ctrl 44 - qcom,sm8450-dsi-ctrl 45 - qcom,sm8550-dsi-ctrl 46 - qcom,sm8650-dsi-ctrl 47 - qcom,sm8750-dsi-ctrl 48 - const: qcom,mdss-dsi-ctrl 49 - items: 50 - enum: 51 - qcom,qcs8300-dsi-ctrl 52 - const: qcom,sa8775p-dsi-ctrl 53 - const: qcom,mdss-dsi-ctrl 54 - enum: 55 - qcom,dsi-ctrl-6g-qcm2290 56 - qcom,mdss-dsi-ctrl # This should always come with an SoC-specific compatible 57 deprecated: true 58 59 reg: 60 maxItems: 1 61 62 reg-names: 63 const: dsi_ctrl 64 65 interrupts: 66 maxItems: 1 67 68 clocks: 69 description: | 70 Several clocks are used, depending on the variant. Typical ones are:: 71 - bus:: Display AHB clock. 72 - byte:: Display byte clock. 73 - byte_intf:: Display byte interface clock. 74 - core:: Display core clock. 75 - core_mss:: Core MultiMedia SubSystem clock. 76 - iface:: Display AXI clock. 77 - mdp_core:: MDP Core clock. 78 - mnoc:: MNOC clock 79 - pixel:: Display pixel clock. 80 minItems: 3 81 maxItems: 12 82 83 clock-names: 84 minItems: 3 85 maxItems: 12 86 87 phys: 88 maxItems: 1 89 90 phy-names: 91 deprecated: true 92 const: dsi 93 94 syscon-sfpb: 95 description: A phandle to mmss_sfpb syscon node (only for DSIv2). 96 $ref: /schemas/types.yaml#/definitions/phandle 97 98 qcom,dual-dsi-mode: 99 type: boolean 100 description: | 101 Indicates if the DSI controller is driving a panel which needs 102 2 DSI links. 103 104 qcom,master-dsi: 105 type: boolean 106 description: | 107 Indicates if the DSI controller is the master DSI controller when 108 qcom,dual-dsi-mode enabled. 109 110 qcom,sync-dual-dsi: 111 type: boolean 112 description: | 113 Indicates if the DSI controller needs to sync the other DSI controller 114 with MIPI DCS commands when qcom,dual-dsi-mode enabled. 115 116 assigned-clocks: 117 minItems: 2 118 maxItems: 4 119 description: | 120 For DSI on SM8650 and older: parents of "byte" and "pixel" for the given 121 platform. 122 For DSIv2 platforms this should contain "byte", "esc", "src" and 123 "pixel_src" clocks. 124 125 assigned-clock-parents: 126 minItems: 2 127 maxItems: 4 128 description: | 129 The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block. 130 131 power-domains: 132 maxItems: 1 133 134 operating-points-v2: true 135 136 opp-table: 137 type: object 138 139 ports: 140 $ref: /schemas/graph.yaml#/properties/ports 141 description: | 142 Contains DSI controller input and output ports as children, each 143 containing one endpoint subnode. 144 145 properties: 146 port@0: 147 $ref: /schemas/graph.yaml#/$defs/port-base 148 unevaluatedProperties: false 149 description: | 150 Input endpoints of the controller. 151 properties: 152 endpoint: 153 $ref: /schemas/media/video-interfaces.yaml# 154 unevaluatedProperties: false 155 properties: 156 data-lanes: 157 maxItems: 4 158 minItems: 1 159 items: 160 enum: [ 0, 1, 2, 3 ] 161 162 port@1: 163 $ref: /schemas/graph.yaml#/$defs/port-base 164 unevaluatedProperties: false 165 description: | 166 Output endpoints of the controller. 167 properties: 168 endpoint: 169 $ref: /schemas/media/video-interfaces.yaml# 170 unevaluatedProperties: false 171 properties: 172 data-lanes: 173 maxItems: 4 174 minItems: 1 175 items: 176 enum: [ 0, 1, 2, 3 ] 177 178 qcom,te-source: 179 $ref: /schemas/types.yaml#/definitions/string 180 description: 181 Specifies the source of vsync signal from the panel used for 182 tearing elimination. 183 default: mdp_vsync_p 184 enum: 185 - mdp_vsync_p 186 - mdp_vsync_s 187 - mdp_vsync_e 188 - timer0 189 - timer1 190 - timer2 191 - timer3 192 - timer4 193 194 required: 195 - port@0 196 - port@1 197 198 avdd-supply: 199 description: 200 Phandle to vdd regulator device node 201 202 refgen-supply: 203 description: 204 Phandle to REFGEN regulator device node 205 206 vcca-supply: 207 description: 208 Phandle to vdd regulator device node 209 210 vdd-supply: 211 description: 212 VDD regulator 213 214 vddio-supply: 215 description: 216 VDD-IO regulator 217 218 vdda-supply: 219 description: 220 VDDA regulator 221 222required: 223 - compatible 224 - reg 225 - reg-names 226 - interrupts 227 - clocks 228 - clock-names 229 - phys 230 - ports 231 232allOf: 233 - $ref: ../dsi-controller.yaml# 234 - if: 235 properties: 236 compatible: 237 contains: 238 enum: 239 - qcom,apq8064-dsi-ctrl 240 then: 241 properties: 242 clocks: 243 minItems: 7 244 maxItems: 7 245 clock-names: 246 items: 247 - const: iface 248 - const: bus 249 - const: core_mmss 250 - const: src 251 - const: byte 252 - const: pixel 253 - const: core 254 required: 255 - assigned-clocks 256 - assigned-clock-parents 257 258 - if: 259 properties: 260 compatible: 261 contains: 262 enum: 263 - qcom,msm8916-dsi-ctrl 264 - qcom,msm8953-dsi-ctrl 265 - qcom,msm8976-dsi-ctrl 266 then: 267 properties: 268 clocks: 269 minItems: 6 270 maxItems: 6 271 clock-names: 272 items: 273 - const: mdp_core 274 - const: iface 275 - const: bus 276 - const: byte 277 - const: pixel 278 - const: core 279 required: 280 - assigned-clocks 281 - assigned-clock-parents 282 283 - if: 284 properties: 285 compatible: 286 contains: 287 enum: 288 - qcom,msm8226-dsi-ctrl 289 - qcom,msm8974-dsi-ctrl 290 then: 291 properties: 292 clocks: 293 minItems: 7 294 maxItems: 7 295 clock-names: 296 items: 297 - const: mdp_core 298 - const: iface 299 - const: bus 300 - const: byte 301 - const: pixel 302 - const: core 303 - const: core_mmss 304 required: 305 - assigned-clocks 306 - assigned-clock-parents 307 308 - if: 309 properties: 310 compatible: 311 contains: 312 enum: 313 - qcom,msm8996-dsi-ctrl 314 then: 315 properties: 316 clocks: 317 minItems: 7 318 maxItems: 7 319 clock-names: 320 items: 321 - const: mdp_core 322 - const: byte 323 - const: iface 324 - const: bus 325 - const: core_mmss 326 - const: pixel 327 - const: core 328 required: 329 - assigned-clocks 330 - assigned-clock-parents 331 332 - if: 333 properties: 334 compatible: 335 contains: 336 enum: 337 - qcom,msm8998-dsi-ctrl 338 - qcom,sa8775p-dsi-ctrl 339 - qcom,sar2130p-dsi-ctrl 340 - qcom,sc7180-dsi-ctrl 341 - qcom,sc7280-dsi-ctrl 342 - qcom,sc8180x-dsi-ctrl 343 - qcom,sdm845-dsi-ctrl 344 - qcom,sm6115-dsi-ctrl 345 - qcom,sm6125-dsi-ctrl 346 - qcom,sm6350-dsi-ctrl 347 - qcom,sm6375-dsi-ctrl 348 - qcom,sm6150-dsi-ctrl 349 - qcom,sm7150-dsi-ctrl 350 - qcom,sm8150-dsi-ctrl 351 - qcom,sm8250-dsi-ctrl 352 - qcom,sm8350-dsi-ctrl 353 - qcom,sm8450-dsi-ctrl 354 - qcom,sm8550-dsi-ctrl 355 - qcom,sm8650-dsi-ctrl 356 then: 357 properties: 358 clocks: 359 minItems: 6 360 maxItems: 6 361 clock-names: 362 items: 363 - const: byte 364 - const: byte_intf 365 - const: pixel 366 - const: core 367 - const: iface 368 - const: bus 369 required: 370 - assigned-clocks 371 - assigned-clock-parents 372 373 - if: 374 properties: 375 compatible: 376 contains: 377 enum: 378 - qcom,kaanapali-dsi-ctrl 379 - qcom,sm8750-dsi-ctrl 380 then: 381 properties: 382 clocks: 383 minItems: 12 384 maxItems: 12 385 clock-names: 386 items: 387 - const: byte 388 - const: byte_intf 389 - const: pixel 390 - const: core 391 - const: iface 392 - const: bus 393 - const: dsi_pll_pixel 394 - const: dsi_pll_byte 395 - const: esync 396 - const: osc 397 - const: byte_src 398 - const: pixel_src 399 400 - if: 401 properties: 402 compatible: 403 contains: 404 enum: 405 - qcom,sdm660-dsi-ctrl 406 then: 407 properties: 408 clocks: 409 minItems: 9 410 maxItems: 9 411 clock-names: 412 items: 413 - const: mdp_core 414 - const: byte 415 - const: byte_intf 416 - const: mnoc 417 - const: iface 418 - const: bus 419 - const: core_mmss 420 - const: pixel 421 - const: core 422 required: 423 - assigned-clocks 424 - assigned-clock-parents 425 426unevaluatedProperties: false 427 428examples: 429 - | 430 #include <dt-bindings/interrupt-controller/arm-gic.h> 431 #include <dt-bindings/clock/qcom,dispcc-sdm845.h> 432 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 433 #include <dt-bindings/power/qcom-rpmpd.h> 434 435 dsi@ae94000 { 436 compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 437 reg = <0x0ae94000 0x400>; 438 reg-names = "dsi_ctrl"; 439 440 #address-cells = <1>; 441 #size-cells = <0>; 442 443 interrupt-parent = <&mdss>; 444 interrupts = <4>; 445 446 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 447 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 448 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 449 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 450 <&dispcc DISP_CC_MDSS_AHB_CLK>, 451 <&dispcc DISP_CC_MDSS_AXI_CLK>; 452 clock-names = "byte", 453 "byte_intf", 454 "pixel", 455 "core", 456 "iface", 457 "bus"; 458 459 phys = <&dsi0_phy>; 460 phy-names = "dsi"; 461 462 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 463 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>; 464 465 power-domains = <&rpmhpd SC7180_CX>; 466 operating-points-v2 = <&dsi_opp_table>; 467 468 ports { 469 #address-cells = <1>; 470 #size-cells = <0>; 471 472 port@0 { 473 reg = <0>; 474 endpoint { 475 remote-endpoint = <&dpu_intf1_out>; 476 }; 477 }; 478 479 port@1 { 480 reg = <1>; 481 endpoint { 482 remote-endpoint = <&sn65dsi86_in>; 483 data-lanes = <0 1 2 3>; 484 qcom,te-source = "mdp_vsync_e"; 485 }; 486 }; 487 }; 488 }; 489... 490