1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Display DSI controller 8 9maintainers: 10 - Krishna Manikandan <quic_mkrishn@quicinc.com> 11 12properties: 13 compatible: 14 oneOf: 15 - items: 16 - enum: 17 - qcom,apq8064-dsi-ctrl 18 - qcom,kaanapali-dsi-ctrl 19 - qcom,milos-dsi-ctrl 20 - qcom,msm8226-dsi-ctrl 21 - qcom,msm8916-dsi-ctrl 22 - qcom,msm8953-dsi-ctrl 23 - qcom,msm8974-dsi-ctrl 24 - qcom,msm8976-dsi-ctrl 25 - qcom,msm8996-dsi-ctrl 26 - qcom,msm8998-dsi-ctrl 27 - qcom,qcm2290-dsi-ctrl 28 - qcom,sa8775p-dsi-ctrl 29 - qcom,sar2130p-dsi-ctrl 30 - qcom,sc7180-dsi-ctrl 31 - qcom,sc7280-dsi-ctrl 32 - qcom,sc8180x-dsi-ctrl 33 - qcom,sdm660-dsi-ctrl 34 - qcom,sdm670-dsi-ctrl 35 - qcom,sdm845-dsi-ctrl 36 - qcom,sm6115-dsi-ctrl 37 - qcom,sm6125-dsi-ctrl 38 - qcom,sm6150-dsi-ctrl 39 - qcom,sm6350-dsi-ctrl 40 - qcom,sm6375-dsi-ctrl 41 - qcom,sm7150-dsi-ctrl 42 - qcom,sm8150-dsi-ctrl 43 - qcom,sm8250-dsi-ctrl 44 - qcom,sm8350-dsi-ctrl 45 - qcom,sm8450-dsi-ctrl 46 - qcom,sm8550-dsi-ctrl 47 - qcom,sm8650-dsi-ctrl 48 - qcom,sm8750-dsi-ctrl 49 - const: qcom,mdss-dsi-ctrl 50 - items: 51 - enum: 52 - qcom,qcs8300-dsi-ctrl 53 - qcom,sc8280xp-dsi-ctrl 54 - const: qcom,sa8775p-dsi-ctrl 55 - const: qcom,mdss-dsi-ctrl 56 - items: 57 - const: qcom,eliza-dsi-ctrl 58 - const: qcom,sm8750-dsi-ctrl 59 - const: qcom,mdss-dsi-ctrl 60 - enum: 61 - qcom,dsi-ctrl-6g-qcm2290 62 - qcom,mdss-dsi-ctrl # This should always come with an SoC-specific compatible 63 deprecated: true 64 65 reg: 66 maxItems: 1 67 68 reg-names: 69 const: dsi_ctrl 70 71 interrupts: 72 maxItems: 1 73 74 clocks: 75 description: | 76 Several clocks are used, depending on the variant. Typical ones are:: 77 - bus:: Display AHB clock. 78 - byte:: Display byte clock. 79 - byte_intf:: Display byte interface clock. 80 - core:: Display core clock. 81 - core_mss:: Core MultiMedia SubSystem clock. 82 - iface:: Display AXI clock. 83 - mdp_core:: MDP Core clock. 84 - mnoc:: MNOC clock 85 - pixel:: Display pixel clock. 86 minItems: 3 87 maxItems: 12 88 89 clock-names: 90 minItems: 3 91 maxItems: 12 92 93 phys: 94 maxItems: 1 95 96 phy-names: 97 deprecated: true 98 const: dsi 99 100 syscon-sfpb: 101 description: A phandle to mmss_sfpb syscon node (only for DSIv2). 102 $ref: /schemas/types.yaml#/definitions/phandle 103 104 qcom,dual-dsi-mode: 105 type: boolean 106 description: | 107 Indicates if the DSI controller is driving a panel which needs 108 2 DSI links. 109 110 qcom,master-dsi: 111 type: boolean 112 description: | 113 Indicates if the DSI controller is the master DSI controller when 114 qcom,dual-dsi-mode enabled. 115 116 qcom,sync-dual-dsi: 117 type: boolean 118 description: | 119 Indicates if the DSI controller needs to sync the other DSI controller 120 with MIPI DCS commands when qcom,dual-dsi-mode enabled. 121 122 assigned-clocks: 123 minItems: 2 124 maxItems: 4 125 description: | 126 For DSI on SM8650 and older: parents of "byte" and "pixel" for the given 127 platform. 128 For DSIv2 platforms this should contain "byte", "esc", "src" and 129 "pixel_src" clocks. 130 131 assigned-clock-parents: 132 minItems: 2 133 maxItems: 4 134 description: | 135 The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block. 136 137 power-domains: 138 maxItems: 1 139 140 operating-points-v2: true 141 142 opp-table: 143 type: object 144 145 ports: 146 $ref: /schemas/graph.yaml#/properties/ports 147 description: | 148 Contains DSI controller input and output ports as children, each 149 containing one endpoint subnode. 150 151 properties: 152 port@0: 153 $ref: /schemas/graph.yaml#/$defs/port-base 154 unevaluatedProperties: false 155 description: | 156 Input endpoints of the controller. 157 properties: 158 endpoint: 159 $ref: /schemas/media/video-interfaces.yaml# 160 unevaluatedProperties: false 161 properties: 162 data-lanes: 163 maxItems: 4 164 minItems: 1 165 items: 166 enum: [ 0, 1, 2, 3 ] 167 168 port@1: 169 $ref: /schemas/graph.yaml#/$defs/port-base 170 unevaluatedProperties: false 171 description: | 172 Output endpoints of the controller. 173 properties: 174 endpoint: 175 $ref: /schemas/media/video-interfaces.yaml# 176 unevaluatedProperties: false 177 properties: 178 data-lanes: 179 maxItems: 4 180 minItems: 1 181 items: 182 enum: [ 0, 1, 2, 3 ] 183 184 qcom,te-source: 185 $ref: /schemas/types.yaml#/definitions/string 186 description: 187 Specifies the source of vsync signal from the panel used for 188 tearing elimination. 189 default: mdp_vsync_p 190 enum: 191 - mdp_vsync_p 192 - mdp_vsync_s 193 - mdp_vsync_e 194 - timer0 195 - timer1 196 - timer2 197 - timer3 198 - timer4 199 200 required: 201 - port@0 202 - port@1 203 204 avdd-supply: 205 description: 206 Phandle to vdd regulator device node 207 208 refgen-supply: 209 description: 210 Phandle to REFGEN regulator device node 211 212 vcca-supply: 213 description: 214 Phandle to vdd regulator device node 215 216 vdd-supply: 217 description: 218 VDD regulator 219 220 vddio-supply: 221 description: 222 VDD-IO regulator 223 224 vdda-supply: 225 description: 226 VDDA regulator 227 228required: 229 - compatible 230 - reg 231 - reg-names 232 - interrupts 233 - clocks 234 - clock-names 235 - phys 236 - ports 237 238allOf: 239 - $ref: ../dsi-controller.yaml# 240 - if: 241 properties: 242 compatible: 243 contains: 244 enum: 245 - qcom,apq8064-dsi-ctrl 246 then: 247 properties: 248 clocks: 249 minItems: 7 250 maxItems: 7 251 clock-names: 252 items: 253 - const: iface 254 - const: bus 255 - const: core_mmss 256 - const: src 257 - const: byte 258 - const: pixel 259 - const: core 260 required: 261 - assigned-clocks 262 - assigned-clock-parents 263 264 - if: 265 properties: 266 compatible: 267 contains: 268 enum: 269 - qcom,msm8916-dsi-ctrl 270 - qcom,msm8953-dsi-ctrl 271 - qcom,msm8976-dsi-ctrl 272 then: 273 properties: 274 clocks: 275 minItems: 6 276 maxItems: 6 277 clock-names: 278 items: 279 - const: mdp_core 280 - const: iface 281 - const: bus 282 - const: byte 283 - const: pixel 284 - const: core 285 required: 286 - assigned-clocks 287 - assigned-clock-parents 288 289 - if: 290 properties: 291 compatible: 292 contains: 293 enum: 294 - qcom,msm8226-dsi-ctrl 295 - qcom,msm8974-dsi-ctrl 296 then: 297 properties: 298 clocks: 299 minItems: 7 300 maxItems: 7 301 clock-names: 302 items: 303 - const: mdp_core 304 - const: iface 305 - const: bus 306 - const: byte 307 - const: pixel 308 - const: core 309 - const: core_mmss 310 required: 311 - assigned-clocks 312 - assigned-clock-parents 313 314 - if: 315 properties: 316 compatible: 317 contains: 318 enum: 319 - qcom,msm8996-dsi-ctrl 320 then: 321 properties: 322 clocks: 323 minItems: 7 324 maxItems: 7 325 clock-names: 326 items: 327 - const: mdp_core 328 - const: byte 329 - const: iface 330 - const: bus 331 - const: core_mmss 332 - const: pixel 333 - const: core 334 required: 335 - assigned-clocks 336 - assigned-clock-parents 337 338 - if: 339 properties: 340 compatible: 341 contains: 342 enum: 343 - qcom,milos-dsi-ctrl 344 - qcom,msm8998-dsi-ctrl 345 - qcom,sa8775p-dsi-ctrl 346 - qcom,sar2130p-dsi-ctrl 347 - qcom,sc7180-dsi-ctrl 348 - qcom,sc7280-dsi-ctrl 349 - qcom,sc8180x-dsi-ctrl 350 - qcom,sdm845-dsi-ctrl 351 - qcom,sm6115-dsi-ctrl 352 - qcom,sm6125-dsi-ctrl 353 - qcom,sm6350-dsi-ctrl 354 - qcom,sm6375-dsi-ctrl 355 - qcom,sm6150-dsi-ctrl 356 - qcom,sm7150-dsi-ctrl 357 - qcom,sm8150-dsi-ctrl 358 - qcom,sm8250-dsi-ctrl 359 - qcom,sm8350-dsi-ctrl 360 - qcom,sm8450-dsi-ctrl 361 - qcom,sm8550-dsi-ctrl 362 - qcom,sm8650-dsi-ctrl 363 then: 364 properties: 365 clocks: 366 minItems: 6 367 maxItems: 6 368 clock-names: 369 items: 370 - const: byte 371 - const: byte_intf 372 - const: pixel 373 - const: core 374 - const: iface 375 - const: bus 376 required: 377 - assigned-clocks 378 - assigned-clock-parents 379 380 - if: 381 properties: 382 compatible: 383 contains: 384 enum: 385 - qcom,kaanapali-dsi-ctrl 386 - qcom,sm8750-dsi-ctrl 387 then: 388 properties: 389 clocks: 390 minItems: 12 391 maxItems: 12 392 clock-names: 393 items: 394 - const: byte 395 - const: byte_intf 396 - const: pixel 397 - const: core 398 - const: iface 399 - const: bus 400 - const: dsi_pll_pixel 401 - const: dsi_pll_byte 402 - const: esync 403 - const: osc 404 - const: byte_src 405 - const: pixel_src 406 407 - if: 408 properties: 409 compatible: 410 contains: 411 enum: 412 - qcom,sdm660-dsi-ctrl 413 then: 414 properties: 415 clocks: 416 minItems: 9 417 maxItems: 9 418 clock-names: 419 items: 420 - const: mdp_core 421 - const: byte 422 - const: byte_intf 423 - const: mnoc 424 - const: iface 425 - const: bus 426 - const: core_mmss 427 - const: pixel 428 - const: core 429 required: 430 - assigned-clocks 431 - assigned-clock-parents 432 433unevaluatedProperties: false 434 435examples: 436 - | 437 #include <dt-bindings/interrupt-controller/arm-gic.h> 438 #include <dt-bindings/clock/qcom,dispcc-sdm845.h> 439 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 440 #include <dt-bindings/power/qcom-rpmpd.h> 441 442 dsi@ae94000 { 443 compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 444 reg = <0x0ae94000 0x400>; 445 reg-names = "dsi_ctrl"; 446 447 #address-cells = <1>; 448 #size-cells = <0>; 449 450 interrupt-parent = <&mdss>; 451 interrupts = <4>; 452 453 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 454 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 455 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 456 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 457 <&dispcc DISP_CC_MDSS_AHB_CLK>, 458 <&dispcc DISP_CC_MDSS_AXI_CLK>; 459 clock-names = "byte", 460 "byte_intf", 461 "pixel", 462 "core", 463 "iface", 464 "bus"; 465 466 phys = <&dsi0_phy>; 467 phy-names = "dsi"; 468 469 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 470 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>; 471 472 power-domains = <&rpmhpd SC7180_CX>; 473 operating-points-v2 = <&dsi_opp_table>; 474 475 ports { 476 #address-cells = <1>; 477 #size-cells = <0>; 478 479 port@0 { 480 reg = <0>; 481 endpoint { 482 remote-endpoint = <&dpu_intf1_out>; 483 }; 484 }; 485 486 port@1 { 487 reg = <1>; 488 endpoint { 489 remote-endpoint = <&sn65dsi86_in>; 490 data-lanes = <0 1 2 3>; 491 qcom,te-source = "mdp_vsync_e"; 492 }; 493 }; 494 }; 495 }; 496... 497