1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Display DSI controller 8 9maintainers: 10 - Krishna Manikandan <quic_mkrishn@quicinc.com> 11 12properties: 13 compatible: 14 oneOf: 15 - items: 16 - enum: 17 - qcom,apq8064-dsi-ctrl 18 - qcom,msm8226-dsi-ctrl 19 - qcom,msm8916-dsi-ctrl 20 - qcom,msm8953-dsi-ctrl 21 - qcom,msm8974-dsi-ctrl 22 - qcom,msm8976-dsi-ctrl 23 - qcom,msm8996-dsi-ctrl 24 - qcom,msm8998-dsi-ctrl 25 - qcom,qcm2290-dsi-ctrl 26 - qcom,sa8775p-dsi-ctrl 27 - qcom,sar2130p-dsi-ctrl 28 - qcom,sc7180-dsi-ctrl 29 - qcom,sc7280-dsi-ctrl 30 - qcom,sdm660-dsi-ctrl 31 - qcom,sdm670-dsi-ctrl 32 - qcom,sdm845-dsi-ctrl 33 - qcom,sm6115-dsi-ctrl 34 - qcom,sm6125-dsi-ctrl 35 - qcom,sm6150-dsi-ctrl 36 - qcom,sm6350-dsi-ctrl 37 - qcom,sm6375-dsi-ctrl 38 - qcom,sm7150-dsi-ctrl 39 - qcom,sm8150-dsi-ctrl 40 - qcom,sm8250-dsi-ctrl 41 - qcom,sm8350-dsi-ctrl 42 - qcom,sm8450-dsi-ctrl 43 - qcom,sm8550-dsi-ctrl 44 - qcom,sm8650-dsi-ctrl 45 - qcom,sm8750-dsi-ctrl 46 - const: qcom,mdss-dsi-ctrl 47 - enum: 48 - qcom,dsi-ctrl-6g-qcm2290 49 - qcom,mdss-dsi-ctrl # This should always come with an SoC-specific compatible 50 deprecated: true 51 52 reg: 53 maxItems: 1 54 55 reg-names: 56 const: dsi_ctrl 57 58 interrupts: 59 maxItems: 1 60 61 clocks: 62 description: | 63 Several clocks are used, depending on the variant. Typical ones are:: 64 - bus:: Display AHB clock. 65 - byte:: Display byte clock. 66 - byte_intf:: Display byte interface clock. 67 - core:: Display core clock. 68 - core_mss:: Core MultiMedia SubSystem clock. 69 - iface:: Display AXI clock. 70 - mdp_core:: MDP Core clock. 71 - mnoc:: MNOC clock 72 - pixel:: Display pixel clock. 73 minItems: 3 74 maxItems: 12 75 76 clock-names: 77 minItems: 3 78 maxItems: 12 79 80 phys: 81 maxItems: 1 82 83 phy-names: 84 deprecated: true 85 const: dsi 86 87 syscon-sfpb: 88 description: A phandle to mmss_sfpb syscon node (only for DSIv2). 89 $ref: /schemas/types.yaml#/definitions/phandle 90 91 qcom,dual-dsi-mode: 92 type: boolean 93 description: | 94 Indicates if the DSI controller is driving a panel which needs 95 2 DSI links. 96 97 qcom,master-dsi: 98 type: boolean 99 description: | 100 Indicates if the DSI controller is the master DSI controller when 101 qcom,dual-dsi-mode enabled. 102 103 qcom,sync-dual-dsi: 104 type: boolean 105 description: | 106 Indicates if the DSI controller needs to sync the other DSI controller 107 with MIPI DCS commands when qcom,dual-dsi-mode enabled. 108 109 assigned-clocks: 110 minItems: 2 111 maxItems: 4 112 description: | 113 For DSI on SM8650 and older: parents of "byte" and "pixel" for the given 114 platform. 115 For DSIv2 platforms this should contain "byte", "esc", "src" and 116 "pixel_src" clocks. 117 118 assigned-clock-parents: 119 minItems: 2 120 maxItems: 4 121 description: | 122 The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block. 123 124 power-domains: 125 maxItems: 1 126 127 operating-points-v2: true 128 129 opp-table: 130 type: object 131 132 ports: 133 $ref: /schemas/graph.yaml#/properties/ports 134 description: | 135 Contains DSI controller input and output ports as children, each 136 containing one endpoint subnode. 137 138 properties: 139 port@0: 140 $ref: /schemas/graph.yaml#/$defs/port-base 141 unevaluatedProperties: false 142 description: | 143 Input endpoints of the controller. 144 properties: 145 endpoint: 146 $ref: /schemas/media/video-interfaces.yaml# 147 unevaluatedProperties: false 148 properties: 149 data-lanes: 150 maxItems: 4 151 minItems: 1 152 items: 153 enum: [ 0, 1, 2, 3 ] 154 155 port@1: 156 $ref: /schemas/graph.yaml#/$defs/port-base 157 unevaluatedProperties: false 158 description: | 159 Output endpoints of the controller. 160 properties: 161 endpoint: 162 $ref: /schemas/media/video-interfaces.yaml# 163 unevaluatedProperties: false 164 properties: 165 data-lanes: 166 maxItems: 4 167 minItems: 1 168 items: 169 enum: [ 0, 1, 2, 3 ] 170 171 qcom,te-source: 172 $ref: /schemas/types.yaml#/definitions/string 173 description: 174 Specifies the source of vsync signal from the panel used for 175 tearing elimination. 176 default: mdp_vsync_p 177 enum: 178 - mdp_vsync_p 179 - mdp_vsync_s 180 - mdp_vsync_e 181 - timer0 182 - timer1 183 - timer2 184 - timer3 185 - timer4 186 187 required: 188 - port@0 189 - port@1 190 191 avdd-supply: 192 description: 193 Phandle to vdd regulator device node 194 195 refgen-supply: 196 description: 197 Phandle to REFGEN regulator device node 198 199 vcca-supply: 200 description: 201 Phandle to vdd regulator device node 202 203 vdd-supply: 204 description: 205 VDD regulator 206 207 vddio-supply: 208 description: 209 VDD-IO regulator 210 211 vdda-supply: 212 description: 213 VDDA regulator 214 215required: 216 - compatible 217 - reg 218 - reg-names 219 - interrupts 220 - clocks 221 - clock-names 222 - phys 223 - ports 224 225allOf: 226 - $ref: ../dsi-controller.yaml# 227 - if: 228 properties: 229 compatible: 230 contains: 231 enum: 232 - qcom,apq8064-dsi-ctrl 233 then: 234 properties: 235 clocks: 236 minItems: 7 237 maxItems: 7 238 clock-names: 239 items: 240 - const: iface 241 - const: bus 242 - const: core_mmss 243 - const: src 244 - const: byte 245 - const: pixel 246 - const: core 247 required: 248 - assigned-clocks 249 - assigned-clock-parents 250 251 - if: 252 properties: 253 compatible: 254 contains: 255 enum: 256 - qcom,msm8916-dsi-ctrl 257 - qcom,msm8953-dsi-ctrl 258 - qcom,msm8976-dsi-ctrl 259 then: 260 properties: 261 clocks: 262 minItems: 6 263 maxItems: 6 264 clock-names: 265 items: 266 - const: mdp_core 267 - const: iface 268 - const: bus 269 - const: byte 270 - const: pixel 271 - const: core 272 required: 273 - assigned-clocks 274 - assigned-clock-parents 275 276 - if: 277 properties: 278 compatible: 279 contains: 280 enum: 281 - qcom,msm8226-dsi-ctrl 282 - qcom,msm8974-dsi-ctrl 283 then: 284 properties: 285 clocks: 286 minItems: 7 287 maxItems: 7 288 clock-names: 289 items: 290 - const: mdp_core 291 - const: iface 292 - const: bus 293 - const: byte 294 - const: pixel 295 - const: core 296 - const: core_mmss 297 required: 298 - assigned-clocks 299 - assigned-clock-parents 300 301 - if: 302 properties: 303 compatible: 304 contains: 305 enum: 306 - qcom,msm8996-dsi-ctrl 307 then: 308 properties: 309 clocks: 310 minItems: 7 311 maxItems: 7 312 clock-names: 313 items: 314 - const: mdp_core 315 - const: byte 316 - const: iface 317 - const: bus 318 - const: core_mmss 319 - const: pixel 320 - const: core 321 required: 322 - assigned-clocks 323 - assigned-clock-parents 324 325 - if: 326 properties: 327 compatible: 328 contains: 329 enum: 330 - qcom,msm8998-dsi-ctrl 331 - qcom,sa8775p-dsi-ctrl 332 - qcom,sar2130p-dsi-ctrl 333 - qcom,sc7180-dsi-ctrl 334 - qcom,sc7280-dsi-ctrl 335 - qcom,sdm845-dsi-ctrl 336 - qcom,sm6115-dsi-ctrl 337 - qcom,sm6125-dsi-ctrl 338 - qcom,sm6350-dsi-ctrl 339 - qcom,sm6375-dsi-ctrl 340 - qcom,sm6150-dsi-ctrl 341 - qcom,sm7150-dsi-ctrl 342 - qcom,sm8150-dsi-ctrl 343 - qcom,sm8250-dsi-ctrl 344 - qcom,sm8350-dsi-ctrl 345 - qcom,sm8450-dsi-ctrl 346 - qcom,sm8550-dsi-ctrl 347 - qcom,sm8650-dsi-ctrl 348 then: 349 properties: 350 clocks: 351 minItems: 6 352 maxItems: 6 353 clock-names: 354 items: 355 - const: byte 356 - const: byte_intf 357 - const: pixel 358 - const: core 359 - const: iface 360 - const: bus 361 required: 362 - assigned-clocks 363 - assigned-clock-parents 364 365 - if: 366 properties: 367 compatible: 368 contains: 369 enum: 370 - qcom,sm8750-dsi-ctrl 371 then: 372 properties: 373 clocks: 374 minItems: 12 375 maxItems: 12 376 clock-names: 377 items: 378 - const: byte 379 - const: byte_intf 380 - const: pixel 381 - const: core 382 - const: iface 383 - const: bus 384 - const: dsi_pll_pixel 385 - const: dsi_pll_byte 386 - const: esync 387 - const: osc 388 - const: byte_src 389 - const: pixel_src 390 391 - if: 392 properties: 393 compatible: 394 contains: 395 enum: 396 - qcom,sdm660-dsi-ctrl 397 then: 398 properties: 399 clocks: 400 minItems: 9 401 maxItems: 9 402 clock-names: 403 items: 404 - const: mdp_core 405 - const: byte 406 - const: byte_intf 407 - const: mnoc 408 - const: iface 409 - const: bus 410 - const: core_mmss 411 - const: pixel 412 - const: core 413 required: 414 - assigned-clocks 415 - assigned-clock-parents 416 417unevaluatedProperties: false 418 419examples: 420 - | 421 #include <dt-bindings/interrupt-controller/arm-gic.h> 422 #include <dt-bindings/clock/qcom,dispcc-sdm845.h> 423 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 424 #include <dt-bindings/power/qcom-rpmpd.h> 425 426 dsi@ae94000 { 427 compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 428 reg = <0x0ae94000 0x400>; 429 reg-names = "dsi_ctrl"; 430 431 #address-cells = <1>; 432 #size-cells = <0>; 433 434 interrupt-parent = <&mdss>; 435 interrupts = <4>; 436 437 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 438 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 439 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 440 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 441 <&dispcc DISP_CC_MDSS_AHB_CLK>, 442 <&dispcc DISP_CC_MDSS_AXI_CLK>; 443 clock-names = "byte", 444 "byte_intf", 445 "pixel", 446 "core", 447 "iface", 448 "bus"; 449 450 phys = <&dsi0_phy>; 451 phy-names = "dsi"; 452 453 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 454 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>; 455 456 power-domains = <&rpmhpd SC7180_CX>; 457 operating-points-v2 = <&dsi_opp_table>; 458 459 ports { 460 #address-cells = <1>; 461 #size-cells = <0>; 462 463 port@0 { 464 reg = <0>; 465 endpoint { 466 remote-endpoint = <&dpu_intf1_out>; 467 }; 468 }; 469 470 port@1 { 471 reg = <1>; 472 endpoint { 473 remote-endpoint = <&sn65dsi86_in>; 474 data-lanes = <0 1 2 3>; 475 qcom,te-source = "mdp_vsync_e"; 476 }; 477 }; 478 }; 479 }; 480... 481