1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Display DSI controller 8 9maintainers: 10 - Krishna Manikandan <quic_mkrishn@quicinc.com> 11 12properties: 13 compatible: 14 oneOf: 15 - items: 16 - enum: 17 - qcom,apq8064-dsi-ctrl 18 - qcom,msm8226-dsi-ctrl 19 - qcom,msm8916-dsi-ctrl 20 - qcom,msm8953-dsi-ctrl 21 - qcom,msm8974-dsi-ctrl 22 - qcom,msm8976-dsi-ctrl 23 - qcom,msm8996-dsi-ctrl 24 - qcom,msm8998-dsi-ctrl 25 - qcom,qcm2290-dsi-ctrl 26 - qcom,sc7180-dsi-ctrl 27 - qcom,sc7280-dsi-ctrl 28 - qcom,sdm660-dsi-ctrl 29 - qcom,sdm670-dsi-ctrl 30 - qcom,sdm845-dsi-ctrl 31 - qcom,sm6115-dsi-ctrl 32 - qcom,sm6125-dsi-ctrl 33 - qcom,sm6350-dsi-ctrl 34 - qcom,sm6375-dsi-ctrl 35 - qcom,sm8150-dsi-ctrl 36 - qcom,sm8250-dsi-ctrl 37 - qcom,sm8350-dsi-ctrl 38 - qcom,sm8450-dsi-ctrl 39 - qcom,sm8550-dsi-ctrl 40 - qcom,sm8650-dsi-ctrl 41 - const: qcom,mdss-dsi-ctrl 42 - enum: 43 - qcom,dsi-ctrl-6g-qcm2290 44 - qcom,mdss-dsi-ctrl # This should always come with an SoC-specific compatible 45 deprecated: true 46 47 reg: 48 maxItems: 1 49 50 reg-names: 51 const: dsi_ctrl 52 53 interrupts: 54 maxItems: 1 55 56 clocks: 57 description: | 58 Several clocks are used, depending on the variant. Typical ones are:: 59 - bus:: Display AHB clock. 60 - byte:: Display byte clock. 61 - byte_intf:: Display byte interface clock. 62 - core:: Display core clock. 63 - core_mss:: Core MultiMedia SubSystem clock. 64 - iface:: Display AXI clock. 65 - mdp_core:: MDP Core clock. 66 - mnoc:: MNOC clock 67 - pixel:: Display pixel clock. 68 minItems: 3 69 maxItems: 9 70 71 clock-names: 72 minItems: 3 73 maxItems: 9 74 75 phys: 76 maxItems: 1 77 78 phy-names: 79 deprecated: true 80 const: dsi 81 82 syscon-sfpb: 83 description: A phandle to mmss_sfpb syscon node (only for DSIv2). 84 $ref: /schemas/types.yaml#/definitions/phandle 85 86 qcom,dual-dsi-mode: 87 type: boolean 88 description: | 89 Indicates if the DSI controller is driving a panel which needs 90 2 DSI links. 91 92 qcom,master-dsi: 93 type: boolean 94 description: | 95 Indicates if the DSI controller is the master DSI controller when 96 qcom,dual-dsi-mode enabled. 97 98 qcom,sync-dual-dsi: 99 type: boolean 100 description: | 101 Indicates if the DSI controller needs to sync the other DSI controller 102 with MIPI DCS commands when qcom,dual-dsi-mode enabled. 103 104 assigned-clocks: 105 minItems: 2 106 maxItems: 4 107 description: | 108 Parents of "byte" and "pixel" for the given platform. 109 For DSIv2 platforms this should contain "byte", "esc", "src" and 110 "pixel_src" clocks. 111 112 assigned-clock-parents: 113 minItems: 2 114 maxItems: 4 115 description: | 116 The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block. 117 118 power-domains: 119 maxItems: 1 120 121 operating-points-v2: true 122 123 opp-table: 124 type: object 125 126 ports: 127 $ref: /schemas/graph.yaml#/properties/ports 128 description: | 129 Contains DSI controller input and output ports as children, each 130 containing one endpoint subnode. 131 132 properties: 133 port@0: 134 $ref: /schemas/graph.yaml#/$defs/port-base 135 unevaluatedProperties: false 136 description: | 137 Input endpoints of the controller. 138 properties: 139 endpoint: 140 $ref: /schemas/media/video-interfaces.yaml# 141 unevaluatedProperties: false 142 properties: 143 data-lanes: 144 maxItems: 4 145 minItems: 1 146 items: 147 enum: [ 0, 1, 2, 3 ] 148 149 port@1: 150 $ref: /schemas/graph.yaml#/$defs/port-base 151 unevaluatedProperties: false 152 description: | 153 Output endpoints of the controller. 154 properties: 155 endpoint: 156 $ref: /schemas/media/video-interfaces.yaml# 157 unevaluatedProperties: false 158 properties: 159 data-lanes: 160 maxItems: 4 161 minItems: 1 162 items: 163 enum: [ 0, 1, 2, 3 ] 164 165 required: 166 - port@0 167 - port@1 168 169 avdd-supply: 170 description: 171 Phandle to vdd regulator device node 172 173 refgen-supply: 174 description: 175 Phandle to REFGEN regulator device node 176 177 vcca-supply: 178 description: 179 Phandle to vdd regulator device node 180 181 vdd-supply: 182 description: 183 VDD regulator 184 185 vddio-supply: 186 description: 187 VDD-IO regulator 188 189 vdda-supply: 190 description: 191 VDDA regulator 192 193required: 194 - compatible 195 - reg 196 - reg-names 197 - interrupts 198 - clocks 199 - clock-names 200 - phys 201 - assigned-clocks 202 - assigned-clock-parents 203 - ports 204 205allOf: 206 - $ref: ../dsi-controller.yaml# 207 - if: 208 properties: 209 compatible: 210 contains: 211 enum: 212 - qcom,apq8064-dsi-ctrl 213 then: 214 properties: 215 clocks: 216 maxItems: 7 217 clock-names: 218 items: 219 - const: iface 220 - const: bus 221 - const: core_mmss 222 - const: src 223 - const: byte 224 - const: pixel 225 - const: core 226 227 - if: 228 properties: 229 compatible: 230 contains: 231 enum: 232 - qcom,msm8916-dsi-ctrl 233 then: 234 properties: 235 clocks: 236 maxItems: 6 237 clock-names: 238 items: 239 - const: mdp_core 240 - const: iface 241 - const: bus 242 - const: byte 243 - const: pixel 244 - const: core 245 246 - if: 247 properties: 248 compatible: 249 contains: 250 enum: 251 - qcom,msm8953-dsi-ctrl 252 - qcom,msm8976-dsi-ctrl 253 then: 254 properties: 255 clocks: 256 maxItems: 6 257 clock-names: 258 items: 259 - const: mdp_core 260 - const: iface 261 - const: bus 262 - const: byte 263 - const: pixel 264 - const: core 265 266 - if: 267 properties: 268 compatible: 269 contains: 270 enum: 271 - qcom,msm8226-dsi-ctrl 272 - qcom,msm8974-dsi-ctrl 273 then: 274 properties: 275 clocks: 276 maxItems: 7 277 clock-names: 278 items: 279 - const: mdp_core 280 - const: iface 281 - const: bus 282 - const: byte 283 - const: pixel 284 - const: core 285 - const: core_mmss 286 287 - if: 288 properties: 289 compatible: 290 contains: 291 enum: 292 - qcom,msm8996-dsi-ctrl 293 then: 294 properties: 295 clocks: 296 maxItems: 7 297 clock-names: 298 items: 299 - const: mdp_core 300 - const: byte 301 - const: iface 302 - const: bus 303 - const: core_mmss 304 - const: pixel 305 - const: core 306 307 - if: 308 properties: 309 compatible: 310 contains: 311 enum: 312 - qcom,msm8998-dsi-ctrl 313 - qcom,sm6125-dsi-ctrl 314 - qcom,sm6350-dsi-ctrl 315 then: 316 properties: 317 clocks: 318 maxItems: 6 319 clock-names: 320 items: 321 - const: byte 322 - const: byte_intf 323 - const: pixel 324 - const: core 325 - const: iface 326 - const: bus 327 328 - if: 329 properties: 330 compatible: 331 contains: 332 enum: 333 - qcom,sc7180-dsi-ctrl 334 - qcom,sc7280-dsi-ctrl 335 - qcom,sm8150-dsi-ctrl 336 - qcom,sm8250-dsi-ctrl 337 - qcom,sm8350-dsi-ctrl 338 - qcom,sm8450-dsi-ctrl 339 - qcom,sm8550-dsi-ctrl 340 - qcom,sm8650-dsi-ctrl 341 then: 342 properties: 343 clocks: 344 maxItems: 6 345 clock-names: 346 items: 347 - const: byte 348 - const: byte_intf 349 - const: pixel 350 - const: core 351 - const: iface 352 - const: bus 353 354 - if: 355 properties: 356 compatible: 357 contains: 358 enum: 359 - qcom,sdm660-dsi-ctrl 360 then: 361 properties: 362 clocks: 363 maxItems: 9 364 clock-names: 365 items: 366 - const: mdp_core 367 - const: byte 368 - const: byte_intf 369 - const: mnoc 370 - const: iface 371 - const: bus 372 - const: core_mmss 373 - const: pixel 374 - const: core 375 376 - if: 377 properties: 378 compatible: 379 contains: 380 enum: 381 - qcom,sdm845-dsi-ctrl 382 - qcom,sm6115-dsi-ctrl 383 - qcom,sm6375-dsi-ctrl 384 then: 385 properties: 386 clocks: 387 maxItems: 6 388 clock-names: 389 items: 390 - const: byte 391 - const: byte_intf 392 - const: pixel 393 - const: core 394 - const: iface 395 - const: bus 396 397unevaluatedProperties: false 398 399examples: 400 - | 401 #include <dt-bindings/interrupt-controller/arm-gic.h> 402 #include <dt-bindings/clock/qcom,dispcc-sdm845.h> 403 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 404 #include <dt-bindings/power/qcom-rpmpd.h> 405 406 dsi@ae94000 { 407 compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 408 reg = <0x0ae94000 0x400>; 409 reg-names = "dsi_ctrl"; 410 411 #address-cells = <1>; 412 #size-cells = <0>; 413 414 interrupt-parent = <&mdss>; 415 interrupts = <4>; 416 417 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 418 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 419 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 420 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 421 <&dispcc DISP_CC_MDSS_AHB_CLK>, 422 <&dispcc DISP_CC_MDSS_AXI_CLK>; 423 clock-names = "byte", 424 "byte_intf", 425 "pixel", 426 "core", 427 "iface", 428 "bus"; 429 430 phys = <&dsi0_phy>; 431 phy-names = "dsi"; 432 433 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 434 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>; 435 436 power-domains = <&rpmhpd SC7180_CX>; 437 operating-points-v2 = <&dsi_opp_table>; 438 439 ports { 440 #address-cells = <1>; 441 #size-cells = <0>; 442 443 port@0 { 444 reg = <0>; 445 dsi0_in: endpoint { 446 remote-endpoint = <&dpu_intf1_out>; 447 }; 448 }; 449 450 port@1 { 451 reg = <1>; 452 dsi0_out: endpoint { 453 remote-endpoint = <&sn65dsi86_in>; 454 data-lanes = <0 1 2 3>; 455 }; 456 }; 457 }; 458 }; 459... 460