1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Display DSI controller 8 9maintainers: 10 - Krishna Manikandan <quic_mkrishn@quicinc.com> 11 12properties: 13 compatible: 14 oneOf: 15 - items: 16 - enum: 17 - qcom,apq8064-dsi-ctrl 18 - qcom,kaanapali-dsi-ctrl 19 - qcom,msm8226-dsi-ctrl 20 - qcom,msm8916-dsi-ctrl 21 - qcom,msm8953-dsi-ctrl 22 - qcom,msm8974-dsi-ctrl 23 - qcom,msm8976-dsi-ctrl 24 - qcom,msm8996-dsi-ctrl 25 - qcom,msm8998-dsi-ctrl 26 - qcom,qcm2290-dsi-ctrl 27 - qcom,sa8775p-dsi-ctrl 28 - qcom,sar2130p-dsi-ctrl 29 - qcom,sc7180-dsi-ctrl 30 - qcom,sc7280-dsi-ctrl 31 - qcom,sc8180x-dsi-ctrl 32 - qcom,sdm660-dsi-ctrl 33 - qcom,sdm670-dsi-ctrl 34 - qcom,sdm845-dsi-ctrl 35 - qcom,sm6115-dsi-ctrl 36 - qcom,sm6125-dsi-ctrl 37 - qcom,sm6150-dsi-ctrl 38 - qcom,sm6350-dsi-ctrl 39 - qcom,sm6375-dsi-ctrl 40 - qcom,sm7150-dsi-ctrl 41 - qcom,sm8150-dsi-ctrl 42 - qcom,sm8250-dsi-ctrl 43 - qcom,sm8350-dsi-ctrl 44 - qcom,sm8450-dsi-ctrl 45 - qcom,sm8550-dsi-ctrl 46 - qcom,sm8650-dsi-ctrl 47 - qcom,sm8750-dsi-ctrl 48 - const: qcom,mdss-dsi-ctrl 49 - items: 50 - enum: 51 - qcom,qcs8300-dsi-ctrl 52 - qcom,sc8280xp-dsi-ctrl 53 - const: qcom,sa8775p-dsi-ctrl 54 - const: qcom,mdss-dsi-ctrl 55 - items: 56 - const: qcom,eliza-dsi-ctrl 57 - const: qcom,sm8750-dsi-ctrl 58 - const: qcom,mdss-dsi-ctrl 59 - enum: 60 - qcom,dsi-ctrl-6g-qcm2290 61 - qcom,mdss-dsi-ctrl # This should always come with an SoC-specific compatible 62 deprecated: true 63 64 reg: 65 maxItems: 1 66 67 reg-names: 68 const: dsi_ctrl 69 70 interrupts: 71 maxItems: 1 72 73 clocks: 74 description: | 75 Several clocks are used, depending on the variant. Typical ones are:: 76 - bus:: Display AHB clock. 77 - byte:: Display byte clock. 78 - byte_intf:: Display byte interface clock. 79 - core:: Display core clock. 80 - core_mss:: Core MultiMedia SubSystem clock. 81 - iface:: Display AXI clock. 82 - mdp_core:: MDP Core clock. 83 - mnoc:: MNOC clock 84 - pixel:: Display pixel clock. 85 minItems: 3 86 maxItems: 12 87 88 clock-names: 89 minItems: 3 90 maxItems: 12 91 92 phys: 93 maxItems: 1 94 95 phy-names: 96 deprecated: true 97 const: dsi 98 99 syscon-sfpb: 100 description: A phandle to mmss_sfpb syscon node (only for DSIv2). 101 $ref: /schemas/types.yaml#/definitions/phandle 102 103 qcom,dual-dsi-mode: 104 type: boolean 105 description: | 106 Indicates if the DSI controller is driving a panel which needs 107 2 DSI links. 108 109 qcom,master-dsi: 110 type: boolean 111 description: | 112 Indicates if the DSI controller is the master DSI controller when 113 qcom,dual-dsi-mode enabled. 114 115 qcom,sync-dual-dsi: 116 type: boolean 117 description: | 118 Indicates if the DSI controller needs to sync the other DSI controller 119 with MIPI DCS commands when qcom,dual-dsi-mode enabled. 120 121 assigned-clocks: 122 minItems: 2 123 maxItems: 4 124 description: | 125 For DSI on SM8650 and older: parents of "byte" and "pixel" for the given 126 platform. 127 For DSIv2 platforms this should contain "byte", "esc", "src" and 128 "pixel_src" clocks. 129 130 assigned-clock-parents: 131 minItems: 2 132 maxItems: 4 133 description: | 134 The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block. 135 136 power-domains: 137 maxItems: 1 138 139 operating-points-v2: true 140 141 opp-table: 142 type: object 143 144 ports: 145 $ref: /schemas/graph.yaml#/properties/ports 146 description: | 147 Contains DSI controller input and output ports as children, each 148 containing one endpoint subnode. 149 150 properties: 151 port@0: 152 $ref: /schemas/graph.yaml#/$defs/port-base 153 unevaluatedProperties: false 154 description: | 155 Input endpoints of the controller. 156 properties: 157 endpoint: 158 $ref: /schemas/media/video-interfaces.yaml# 159 unevaluatedProperties: false 160 properties: 161 data-lanes: 162 maxItems: 4 163 minItems: 1 164 items: 165 enum: [ 0, 1, 2, 3 ] 166 167 port@1: 168 $ref: /schemas/graph.yaml#/$defs/port-base 169 unevaluatedProperties: false 170 description: | 171 Output endpoints of the controller. 172 properties: 173 endpoint: 174 $ref: /schemas/media/video-interfaces.yaml# 175 unevaluatedProperties: false 176 properties: 177 data-lanes: 178 maxItems: 4 179 minItems: 1 180 items: 181 enum: [ 0, 1, 2, 3 ] 182 183 qcom,te-source: 184 $ref: /schemas/types.yaml#/definitions/string 185 description: 186 Specifies the source of vsync signal from the panel used for 187 tearing elimination. 188 default: mdp_vsync_p 189 enum: 190 - mdp_vsync_p 191 - mdp_vsync_s 192 - mdp_vsync_e 193 - timer0 194 - timer1 195 - timer2 196 - timer3 197 - timer4 198 199 required: 200 - port@0 201 - port@1 202 203 avdd-supply: 204 description: 205 Phandle to vdd regulator device node 206 207 refgen-supply: 208 description: 209 Phandle to REFGEN regulator device node 210 211 vcca-supply: 212 description: 213 Phandle to vdd regulator device node 214 215 vdd-supply: 216 description: 217 VDD regulator 218 219 vddio-supply: 220 description: 221 VDD-IO regulator 222 223 vdda-supply: 224 description: 225 VDDA regulator 226 227required: 228 - compatible 229 - reg 230 - reg-names 231 - interrupts 232 - clocks 233 - clock-names 234 - phys 235 - ports 236 237allOf: 238 - $ref: ../dsi-controller.yaml# 239 - if: 240 properties: 241 compatible: 242 contains: 243 enum: 244 - qcom,apq8064-dsi-ctrl 245 then: 246 properties: 247 clocks: 248 minItems: 7 249 maxItems: 7 250 clock-names: 251 items: 252 - const: iface 253 - const: bus 254 - const: core_mmss 255 - const: src 256 - const: byte 257 - const: pixel 258 - const: core 259 required: 260 - assigned-clocks 261 - assigned-clock-parents 262 263 - if: 264 properties: 265 compatible: 266 contains: 267 enum: 268 - qcom,msm8916-dsi-ctrl 269 - qcom,msm8953-dsi-ctrl 270 - qcom,msm8976-dsi-ctrl 271 then: 272 properties: 273 clocks: 274 minItems: 6 275 maxItems: 6 276 clock-names: 277 items: 278 - const: mdp_core 279 - const: iface 280 - const: bus 281 - const: byte 282 - const: pixel 283 - const: core 284 required: 285 - assigned-clocks 286 - assigned-clock-parents 287 288 - if: 289 properties: 290 compatible: 291 contains: 292 enum: 293 - qcom,msm8226-dsi-ctrl 294 - qcom,msm8974-dsi-ctrl 295 then: 296 properties: 297 clocks: 298 minItems: 7 299 maxItems: 7 300 clock-names: 301 items: 302 - const: mdp_core 303 - const: iface 304 - const: bus 305 - const: byte 306 - const: pixel 307 - const: core 308 - const: core_mmss 309 required: 310 - assigned-clocks 311 - assigned-clock-parents 312 313 - if: 314 properties: 315 compatible: 316 contains: 317 enum: 318 - qcom,msm8996-dsi-ctrl 319 then: 320 properties: 321 clocks: 322 minItems: 7 323 maxItems: 7 324 clock-names: 325 items: 326 - const: mdp_core 327 - const: byte 328 - const: iface 329 - const: bus 330 - const: core_mmss 331 - const: pixel 332 - const: core 333 required: 334 - assigned-clocks 335 - assigned-clock-parents 336 337 - if: 338 properties: 339 compatible: 340 contains: 341 enum: 342 - qcom,msm8998-dsi-ctrl 343 - qcom,sa8775p-dsi-ctrl 344 - qcom,sar2130p-dsi-ctrl 345 - qcom,sc7180-dsi-ctrl 346 - qcom,sc7280-dsi-ctrl 347 - qcom,sc8180x-dsi-ctrl 348 - qcom,sdm845-dsi-ctrl 349 - qcom,sm6115-dsi-ctrl 350 - qcom,sm6125-dsi-ctrl 351 - qcom,sm6350-dsi-ctrl 352 - qcom,sm6375-dsi-ctrl 353 - qcom,sm6150-dsi-ctrl 354 - qcom,sm7150-dsi-ctrl 355 - qcom,sm8150-dsi-ctrl 356 - qcom,sm8250-dsi-ctrl 357 - qcom,sm8350-dsi-ctrl 358 - qcom,sm8450-dsi-ctrl 359 - qcom,sm8550-dsi-ctrl 360 - qcom,sm8650-dsi-ctrl 361 then: 362 properties: 363 clocks: 364 minItems: 6 365 maxItems: 6 366 clock-names: 367 items: 368 - const: byte 369 - const: byte_intf 370 - const: pixel 371 - const: core 372 - const: iface 373 - const: bus 374 required: 375 - assigned-clocks 376 - assigned-clock-parents 377 378 - if: 379 properties: 380 compatible: 381 contains: 382 enum: 383 - qcom,kaanapali-dsi-ctrl 384 - qcom,sm8750-dsi-ctrl 385 then: 386 properties: 387 clocks: 388 minItems: 12 389 maxItems: 12 390 clock-names: 391 items: 392 - const: byte 393 - const: byte_intf 394 - const: pixel 395 - const: core 396 - const: iface 397 - const: bus 398 - const: dsi_pll_pixel 399 - const: dsi_pll_byte 400 - const: esync 401 - const: osc 402 - const: byte_src 403 - const: pixel_src 404 405 - if: 406 properties: 407 compatible: 408 contains: 409 enum: 410 - qcom,sdm660-dsi-ctrl 411 then: 412 properties: 413 clocks: 414 minItems: 9 415 maxItems: 9 416 clock-names: 417 items: 418 - const: mdp_core 419 - const: byte 420 - const: byte_intf 421 - const: mnoc 422 - const: iface 423 - const: bus 424 - const: core_mmss 425 - const: pixel 426 - const: core 427 required: 428 - assigned-clocks 429 - assigned-clock-parents 430 431unevaluatedProperties: false 432 433examples: 434 - | 435 #include <dt-bindings/interrupt-controller/arm-gic.h> 436 #include <dt-bindings/clock/qcom,dispcc-sdm845.h> 437 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 438 #include <dt-bindings/power/qcom-rpmpd.h> 439 440 dsi@ae94000 { 441 compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 442 reg = <0x0ae94000 0x400>; 443 reg-names = "dsi_ctrl"; 444 445 #address-cells = <1>; 446 #size-cells = <0>; 447 448 interrupt-parent = <&mdss>; 449 interrupts = <4>; 450 451 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 452 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 453 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 454 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 455 <&dispcc DISP_CC_MDSS_AHB_CLK>, 456 <&dispcc DISP_CC_MDSS_AXI_CLK>; 457 clock-names = "byte", 458 "byte_intf", 459 "pixel", 460 "core", 461 "iface", 462 "bus"; 463 464 phys = <&dsi0_phy>; 465 phy-names = "dsi"; 466 467 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 468 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>; 469 470 power-domains = <&rpmhpd SC7180_CX>; 471 operating-points-v2 = <&dsi_opp_table>; 472 473 ports { 474 #address-cells = <1>; 475 #size-cells = <0>; 476 477 port@0 { 478 reg = <0>; 479 endpoint { 480 remote-endpoint = <&dpu_intf1_out>; 481 }; 482 }; 483 484 port@1 { 485 reg = <1>; 486 endpoint { 487 remote-endpoint = <&sn65dsi86_in>; 488 data-lanes = <0 1 2 3>; 489 qcom,te-source = "mdp_vsync_e"; 490 }; 491 }; 492 }; 493 }; 494... 495