1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Display DSI controller 8 9maintainers: 10 - Krishna Manikandan <quic_mkrishn@quicinc.com> 11 12properties: 13 compatible: 14 oneOf: 15 - items: 16 - enum: 17 - qcom,apq8064-dsi-ctrl 18 - qcom,kaanapali-dsi-ctrl 19 - qcom,milos-dsi-ctrl 20 - qcom,msm8226-dsi-ctrl 21 - qcom,msm8916-dsi-ctrl 22 - qcom,msm8953-dsi-ctrl 23 - qcom,msm8974-dsi-ctrl 24 - qcom,msm8976-dsi-ctrl 25 - qcom,msm8996-dsi-ctrl 26 - qcom,msm8998-dsi-ctrl 27 - qcom,qcm2290-dsi-ctrl 28 - qcom,sa8775p-dsi-ctrl 29 - qcom,sar2130p-dsi-ctrl 30 - qcom,sc7180-dsi-ctrl 31 - qcom,sc7280-dsi-ctrl 32 - qcom,sc8180x-dsi-ctrl 33 - qcom,sdm660-dsi-ctrl 34 - qcom,sdm670-dsi-ctrl 35 - qcom,sdm845-dsi-ctrl 36 - qcom,sm6115-dsi-ctrl 37 - qcom,sm6125-dsi-ctrl 38 - qcom,sm6150-dsi-ctrl 39 - qcom,sm6350-dsi-ctrl 40 - qcom,sm6375-dsi-ctrl 41 - qcom,sm7150-dsi-ctrl 42 - qcom,sm8150-dsi-ctrl 43 - qcom,sm8250-dsi-ctrl 44 - qcom,sm8350-dsi-ctrl 45 - qcom,sm8450-dsi-ctrl 46 - qcom,sm8550-dsi-ctrl 47 - qcom,sm8650-dsi-ctrl 48 - qcom,sm8750-dsi-ctrl 49 - const: qcom,mdss-dsi-ctrl 50 - items: 51 - const: qcom,shikra-dsi-ctrl 52 - const: qcom,qcm2290-dsi-ctrl 53 - const: qcom,mdss-dsi-ctrl 54 - items: 55 - enum: 56 - qcom,qcs8300-dsi-ctrl 57 - qcom,sc8280xp-dsi-ctrl 58 - const: qcom,sa8775p-dsi-ctrl 59 - const: qcom,mdss-dsi-ctrl 60 - items: 61 - const: qcom,eliza-dsi-ctrl 62 - const: qcom,sm8750-dsi-ctrl 63 - const: qcom,mdss-dsi-ctrl 64 - enum: 65 - qcom,dsi-ctrl-6g-qcm2290 66 - qcom,mdss-dsi-ctrl # This should always come with an SoC-specific compatible 67 deprecated: true 68 69 reg: 70 maxItems: 1 71 72 reg-names: 73 const: dsi_ctrl 74 75 interrupts: 76 maxItems: 1 77 78 clocks: 79 description: | 80 Several clocks are used, depending on the variant. Typical ones are: 81 - bus: Display AHB clock. 82 - byte: Display byte clock. 83 - byte_intf: Display byte interface clock. 84 - core: Display core clock. 85 - core_mss: Core MultiMedia SubSystem clock. 86 - iface: Display AXI clock. 87 - mdp_core: MDP Core clock. 88 - mnoc: MNOC clock 89 - pixel: Display pixel clock. 90 minItems: 3 91 maxItems: 12 92 93 clock-names: 94 minItems: 3 95 maxItems: 12 96 97 phys: 98 maxItems: 1 99 100 phy-names: 101 deprecated: true 102 const: dsi 103 104 syscon-sfpb: 105 description: A phandle to mmss_sfpb syscon node (only for DSIv2). 106 $ref: /schemas/types.yaml#/definitions/phandle 107 108 qcom,dual-dsi-mode: 109 type: boolean 110 description: | 111 Indicates if the DSI controller is driving a panel which needs 112 2 DSI links. 113 114 qcom,master-dsi: 115 type: boolean 116 description: | 117 Indicates if the DSI controller is the master DSI controller when 118 qcom,dual-dsi-mode enabled. 119 120 qcom,sync-dual-dsi: 121 type: boolean 122 description: | 123 Indicates if the DSI controller needs to sync the other DSI controller 124 with MIPI DCS commands when qcom,dual-dsi-mode enabled. 125 126 assigned-clocks: 127 minItems: 2 128 maxItems: 4 129 description: | 130 For DSI on SM8650 and older: parents of "byte" and "pixel" for the given 131 platform. 132 For DSIv2 platforms this should contain "byte", "esc", "src" and 133 "pixel_src" clocks. 134 135 assigned-clock-parents: 136 minItems: 2 137 maxItems: 4 138 description: | 139 The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block. 140 141 power-domains: 142 maxItems: 1 143 144 operating-points-v2: true 145 146 opp-table: 147 type: object 148 149 ports: 150 $ref: /schemas/graph.yaml#/properties/ports 151 description: | 152 Contains DSI controller input and output ports as children, each 153 containing one endpoint subnode. 154 155 properties: 156 port@0: 157 $ref: /schemas/graph.yaml#/$defs/port-base 158 unevaluatedProperties: false 159 description: | 160 Input endpoints of the controller. 161 properties: 162 endpoint: 163 $ref: /schemas/media/video-interfaces.yaml# 164 unevaluatedProperties: false 165 properties: 166 data-lanes: 167 maxItems: 4 168 minItems: 1 169 items: 170 enum: [ 0, 1, 2, 3 ] 171 172 port@1: 173 $ref: /schemas/graph.yaml#/$defs/port-base 174 unevaluatedProperties: false 175 description: | 176 Output endpoints of the controller. 177 properties: 178 endpoint: 179 $ref: /schemas/media/video-interfaces.yaml# 180 unevaluatedProperties: false 181 properties: 182 data-lanes: 183 maxItems: 4 184 minItems: 1 185 items: 186 enum: [ 0, 1, 2, 3 ] 187 188 qcom,te-source: 189 $ref: /schemas/types.yaml#/definitions/string 190 description: 191 Specifies the source of vsync signal from the panel used for 192 tearing elimination. 193 default: mdp_vsync_p 194 enum: 195 - mdp_vsync_p 196 - mdp_vsync_s 197 - mdp_vsync_e 198 - timer0 199 - timer1 200 - timer2 201 - timer3 202 - timer4 203 204 required: 205 - port@0 206 - port@1 207 208 avdd-supply: 209 description: 210 Phandle to vdd regulator device node 211 212 refgen-supply: 213 description: 214 Phandle to REFGEN regulator device node 215 216 vcca-supply: 217 description: 218 Phandle to vdd regulator device node 219 220 vdd-supply: 221 description: 222 VDD regulator 223 224 vddio-supply: 225 description: 226 VDD-IO regulator 227 228 vdda-supply: 229 description: 230 VDDA regulator 231 232required: 233 - compatible 234 - reg 235 - reg-names 236 - interrupts 237 - clocks 238 - clock-names 239 - phys 240 - ports 241 242allOf: 243 - $ref: ../dsi-controller.yaml# 244 - if: 245 properties: 246 compatible: 247 contains: 248 enum: 249 - qcom,apq8064-dsi-ctrl 250 then: 251 properties: 252 clocks: 253 minItems: 7 254 maxItems: 7 255 clock-names: 256 items: 257 - const: iface 258 - const: bus 259 - const: core_mmss 260 - const: src 261 - const: byte 262 - const: pixel 263 - const: core 264 required: 265 - assigned-clocks 266 - assigned-clock-parents 267 268 - if: 269 properties: 270 compatible: 271 contains: 272 enum: 273 - qcom,msm8916-dsi-ctrl 274 - qcom,msm8953-dsi-ctrl 275 - qcom,msm8976-dsi-ctrl 276 then: 277 properties: 278 clocks: 279 minItems: 6 280 maxItems: 6 281 clock-names: 282 items: 283 - const: mdp_core 284 - const: iface 285 - const: bus 286 - const: byte 287 - const: pixel 288 - const: core 289 required: 290 - assigned-clocks 291 - assigned-clock-parents 292 293 - if: 294 properties: 295 compatible: 296 contains: 297 enum: 298 - qcom,msm8226-dsi-ctrl 299 - qcom,msm8974-dsi-ctrl 300 then: 301 properties: 302 clocks: 303 minItems: 7 304 maxItems: 7 305 clock-names: 306 items: 307 - const: mdp_core 308 - const: iface 309 - const: bus 310 - const: byte 311 - const: pixel 312 - const: core 313 - const: core_mmss 314 required: 315 - assigned-clocks 316 - assigned-clock-parents 317 318 - if: 319 properties: 320 compatible: 321 contains: 322 enum: 323 - qcom,msm8996-dsi-ctrl 324 then: 325 properties: 326 clocks: 327 minItems: 7 328 maxItems: 7 329 clock-names: 330 items: 331 - const: mdp_core 332 - const: byte 333 - const: iface 334 - const: bus 335 - const: core_mmss 336 - const: pixel 337 - const: core 338 required: 339 - assigned-clocks 340 - assigned-clock-parents 341 342 - if: 343 properties: 344 compatible: 345 contains: 346 enum: 347 - qcom,milos-dsi-ctrl 348 - qcom,msm8998-dsi-ctrl 349 - qcom,sa8775p-dsi-ctrl 350 - qcom,sar2130p-dsi-ctrl 351 - qcom,sc7180-dsi-ctrl 352 - qcom,sc7280-dsi-ctrl 353 - qcom,sc8180x-dsi-ctrl 354 - qcom,sdm845-dsi-ctrl 355 - qcom,sm6115-dsi-ctrl 356 - qcom,sm6125-dsi-ctrl 357 - qcom,sm6350-dsi-ctrl 358 - qcom,sm6375-dsi-ctrl 359 - qcom,sm6150-dsi-ctrl 360 - qcom,sm7150-dsi-ctrl 361 - qcom,sm8150-dsi-ctrl 362 - qcom,sm8250-dsi-ctrl 363 - qcom,sm8350-dsi-ctrl 364 - qcom,sm8450-dsi-ctrl 365 - qcom,sm8550-dsi-ctrl 366 - qcom,sm8650-dsi-ctrl 367 then: 368 properties: 369 clocks: 370 minItems: 6 371 maxItems: 6 372 clock-names: 373 items: 374 - const: byte 375 - const: byte_intf 376 - const: pixel 377 - const: core 378 - const: iface 379 - const: bus 380 required: 381 - assigned-clocks 382 - assigned-clock-parents 383 384 - if: 385 properties: 386 compatible: 387 contains: 388 enum: 389 - qcom,kaanapali-dsi-ctrl 390 - qcom,sm8750-dsi-ctrl 391 then: 392 properties: 393 clocks: 394 minItems: 12 395 maxItems: 12 396 clock-names: 397 items: 398 - const: byte 399 - const: byte_intf 400 - const: pixel 401 - const: core 402 - const: iface 403 - const: bus 404 - const: dsi_pll_pixel 405 - const: dsi_pll_byte 406 - const: esync 407 - const: osc 408 - const: byte_src 409 - const: pixel_src 410 411 - if: 412 properties: 413 compatible: 414 contains: 415 enum: 416 - qcom,sdm660-dsi-ctrl 417 then: 418 properties: 419 clocks: 420 minItems: 9 421 maxItems: 9 422 clock-names: 423 items: 424 - const: mdp_core 425 - const: byte 426 - const: byte_intf 427 - const: mnoc 428 - const: iface 429 - const: bus 430 - const: core_mmss 431 - const: pixel 432 - const: core 433 required: 434 - assigned-clocks 435 - assigned-clock-parents 436 437unevaluatedProperties: false 438 439examples: 440 - | 441 #include <dt-bindings/interrupt-controller/arm-gic.h> 442 #include <dt-bindings/clock/qcom,dispcc-sdm845.h> 443 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 444 #include <dt-bindings/power/qcom-rpmpd.h> 445 446 dsi@ae94000 { 447 compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 448 reg = <0x0ae94000 0x400>; 449 reg-names = "dsi_ctrl"; 450 451 #address-cells = <1>; 452 #size-cells = <0>; 453 454 interrupt-parent = <&mdss>; 455 interrupts = <4>; 456 457 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 458 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 459 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 460 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 461 <&dispcc DISP_CC_MDSS_AHB_CLK>, 462 <&dispcc DISP_CC_MDSS_AXI_CLK>; 463 clock-names = "byte", 464 "byte_intf", 465 "pixel", 466 "core", 467 "iface", 468 "bus"; 469 470 phys = <&dsi0_phy>; 471 phy-names = "dsi"; 472 473 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 474 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>; 475 476 power-domains = <&rpmhpd SC7180_CX>; 477 operating-points-v2 = <&dsi_opp_table>; 478 479 ports { 480 #address-cells = <1>; 481 #size-cells = <0>; 482 483 port@0 { 484 reg = <0>; 485 endpoint { 486 remote-endpoint = <&dpu_intf1_out>; 487 }; 488 }; 489 490 port@1 { 491 reg = <1>; 492 endpoint { 493 remote-endpoint = <&sn65dsi86_in>; 494 data-lanes = <0 1 2 3>; 495 qcom,te-source = "mdp_vsync_e"; 496 }; 497 }; 498 }; 499 }; 500... 501