1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Display DSI controller 8 9maintainers: 10 - Krishna Manikandan <quic_mkrishn@quicinc.com> 11 12properties: 13 compatible: 14 oneOf: 15 - items: 16 - enum: 17 - qcom,apq8064-dsi-ctrl 18 - qcom,msm8226-dsi-ctrl 19 - qcom,msm8916-dsi-ctrl 20 - qcom,msm8953-dsi-ctrl 21 - qcom,msm8974-dsi-ctrl 22 - qcom,msm8976-dsi-ctrl 23 - qcom,msm8996-dsi-ctrl 24 - qcom,msm8998-dsi-ctrl 25 - qcom,qcm2290-dsi-ctrl 26 - qcom,sa8775p-dsi-ctrl 27 - qcom,sar2130p-dsi-ctrl 28 - qcom,sc7180-dsi-ctrl 29 - qcom,sc7280-dsi-ctrl 30 - qcom,sdm660-dsi-ctrl 31 - qcom,sdm670-dsi-ctrl 32 - qcom,sdm845-dsi-ctrl 33 - qcom,sm6115-dsi-ctrl 34 - qcom,sm6125-dsi-ctrl 35 - qcom,sm6150-dsi-ctrl 36 - qcom,sm6350-dsi-ctrl 37 - qcom,sm6375-dsi-ctrl 38 - qcom,sm7150-dsi-ctrl 39 - qcom,sm8150-dsi-ctrl 40 - qcom,sm8250-dsi-ctrl 41 - qcom,sm8350-dsi-ctrl 42 - qcom,sm8450-dsi-ctrl 43 - qcom,sm8550-dsi-ctrl 44 - qcom,sm8650-dsi-ctrl 45 - const: qcom,mdss-dsi-ctrl 46 - enum: 47 - qcom,dsi-ctrl-6g-qcm2290 48 - qcom,mdss-dsi-ctrl # This should always come with an SoC-specific compatible 49 deprecated: true 50 51 reg: 52 maxItems: 1 53 54 reg-names: 55 const: dsi_ctrl 56 57 interrupts: 58 maxItems: 1 59 60 clocks: 61 description: | 62 Several clocks are used, depending on the variant. Typical ones are:: 63 - bus:: Display AHB clock. 64 - byte:: Display byte clock. 65 - byte_intf:: Display byte interface clock. 66 - core:: Display core clock. 67 - core_mss:: Core MultiMedia SubSystem clock. 68 - iface:: Display AXI clock. 69 - mdp_core:: MDP Core clock. 70 - mnoc:: MNOC clock 71 - pixel:: Display pixel clock. 72 minItems: 3 73 maxItems: 9 74 75 clock-names: 76 minItems: 3 77 maxItems: 9 78 79 phys: 80 maxItems: 1 81 82 phy-names: 83 deprecated: true 84 const: dsi 85 86 syscon-sfpb: 87 description: A phandle to mmss_sfpb syscon node (only for DSIv2). 88 $ref: /schemas/types.yaml#/definitions/phandle 89 90 qcom,dual-dsi-mode: 91 type: boolean 92 description: | 93 Indicates if the DSI controller is driving a panel which needs 94 2 DSI links. 95 96 qcom,master-dsi: 97 type: boolean 98 description: | 99 Indicates if the DSI controller is the master DSI controller when 100 qcom,dual-dsi-mode enabled. 101 102 qcom,sync-dual-dsi: 103 type: boolean 104 description: | 105 Indicates if the DSI controller needs to sync the other DSI controller 106 with MIPI DCS commands when qcom,dual-dsi-mode enabled. 107 108 assigned-clocks: 109 minItems: 2 110 maxItems: 4 111 description: | 112 Parents of "byte" and "pixel" for the given platform. 113 For DSIv2 platforms this should contain "byte", "esc", "src" and 114 "pixel_src" clocks. 115 116 assigned-clock-parents: 117 minItems: 2 118 maxItems: 4 119 description: | 120 The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block. 121 122 power-domains: 123 maxItems: 1 124 125 operating-points-v2: true 126 127 opp-table: 128 type: object 129 130 ports: 131 $ref: /schemas/graph.yaml#/properties/ports 132 description: | 133 Contains DSI controller input and output ports as children, each 134 containing one endpoint subnode. 135 136 properties: 137 port@0: 138 $ref: /schemas/graph.yaml#/$defs/port-base 139 unevaluatedProperties: false 140 description: | 141 Input endpoints of the controller. 142 properties: 143 endpoint: 144 $ref: /schemas/media/video-interfaces.yaml# 145 unevaluatedProperties: false 146 properties: 147 data-lanes: 148 maxItems: 4 149 minItems: 1 150 items: 151 enum: [ 0, 1, 2, 3 ] 152 153 port@1: 154 $ref: /schemas/graph.yaml#/$defs/port-base 155 unevaluatedProperties: false 156 description: | 157 Output endpoints of the controller. 158 properties: 159 endpoint: 160 $ref: /schemas/media/video-interfaces.yaml# 161 unevaluatedProperties: false 162 properties: 163 data-lanes: 164 maxItems: 4 165 minItems: 1 166 items: 167 enum: [ 0, 1, 2, 3 ] 168 169 qcom,te-source: 170 $ref: /schemas/types.yaml#/definitions/string 171 description: 172 Specifies the source of vsync signal from the panel used for 173 tearing elimination. 174 default: mdp_vsync_p 175 enum: 176 - mdp_vsync_p 177 - mdp_vsync_s 178 - mdp_vsync_e 179 - timer0 180 - timer1 181 - timer2 182 - timer3 183 - timer4 184 185 required: 186 - port@0 187 - port@1 188 189 avdd-supply: 190 description: 191 Phandle to vdd regulator device node 192 193 refgen-supply: 194 description: 195 Phandle to REFGEN regulator device node 196 197 vcca-supply: 198 description: 199 Phandle to vdd regulator device node 200 201 vdd-supply: 202 description: 203 VDD regulator 204 205 vddio-supply: 206 description: 207 VDD-IO regulator 208 209 vdda-supply: 210 description: 211 VDDA regulator 212 213required: 214 - compatible 215 - reg 216 - reg-names 217 - interrupts 218 - clocks 219 - clock-names 220 - phys 221 - assigned-clocks 222 - assigned-clock-parents 223 - ports 224 225allOf: 226 - $ref: ../dsi-controller.yaml# 227 - if: 228 properties: 229 compatible: 230 contains: 231 enum: 232 - qcom,apq8064-dsi-ctrl 233 then: 234 properties: 235 clocks: 236 minItems: 7 237 maxItems: 7 238 clock-names: 239 items: 240 - const: iface 241 - const: bus 242 - const: core_mmss 243 - const: src 244 - const: byte 245 - const: pixel 246 - const: core 247 248 - if: 249 properties: 250 compatible: 251 contains: 252 enum: 253 - qcom,msm8916-dsi-ctrl 254 - qcom,msm8953-dsi-ctrl 255 - qcom,msm8976-dsi-ctrl 256 then: 257 properties: 258 clocks: 259 minItems: 6 260 maxItems: 6 261 clock-names: 262 items: 263 - const: mdp_core 264 - const: iface 265 - const: bus 266 - const: byte 267 - const: pixel 268 - const: core 269 270 - if: 271 properties: 272 compatible: 273 contains: 274 enum: 275 - qcom,msm8226-dsi-ctrl 276 - qcom,msm8974-dsi-ctrl 277 then: 278 properties: 279 clocks: 280 minItems: 7 281 maxItems: 7 282 clock-names: 283 items: 284 - const: mdp_core 285 - const: iface 286 - const: bus 287 - const: byte 288 - const: pixel 289 - const: core 290 - const: core_mmss 291 292 - if: 293 properties: 294 compatible: 295 contains: 296 enum: 297 - qcom,msm8996-dsi-ctrl 298 then: 299 properties: 300 clocks: 301 minItems: 7 302 maxItems: 7 303 clock-names: 304 items: 305 - const: mdp_core 306 - const: byte 307 - const: iface 308 - const: bus 309 - const: core_mmss 310 - const: pixel 311 - const: core 312 313 - if: 314 properties: 315 compatible: 316 contains: 317 enum: 318 - qcom,msm8998-dsi-ctrl 319 - qcom,sa8775p-dsi-ctrl 320 - qcom,sar2130p-dsi-ctrl 321 - qcom,sc7180-dsi-ctrl 322 - qcom,sc7280-dsi-ctrl 323 - qcom,sdm845-dsi-ctrl 324 - qcom,sm6115-dsi-ctrl 325 - qcom,sm6125-dsi-ctrl 326 - qcom,sm6350-dsi-ctrl 327 - qcom,sm6375-dsi-ctrl 328 - qcom,sm6150-dsi-ctrl 329 - qcom,sm7150-dsi-ctrl 330 - qcom,sm8150-dsi-ctrl 331 - qcom,sm8250-dsi-ctrl 332 - qcom,sm8350-dsi-ctrl 333 - qcom,sm8450-dsi-ctrl 334 - qcom,sm8550-dsi-ctrl 335 - qcom,sm8650-dsi-ctrl 336 then: 337 properties: 338 clocks: 339 minItems: 6 340 maxItems: 6 341 clock-names: 342 items: 343 - const: byte 344 - const: byte_intf 345 - const: pixel 346 - const: core 347 - const: iface 348 - const: bus 349 350 - if: 351 properties: 352 compatible: 353 contains: 354 enum: 355 - qcom,sdm660-dsi-ctrl 356 then: 357 properties: 358 clocks: 359 minItems: 9 360 maxItems: 9 361 clock-names: 362 items: 363 - const: mdp_core 364 - const: byte 365 - const: byte_intf 366 - const: mnoc 367 - const: iface 368 - const: bus 369 - const: core_mmss 370 - const: pixel 371 - const: core 372 373unevaluatedProperties: false 374 375examples: 376 - | 377 #include <dt-bindings/interrupt-controller/arm-gic.h> 378 #include <dt-bindings/clock/qcom,dispcc-sdm845.h> 379 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 380 #include <dt-bindings/power/qcom-rpmpd.h> 381 382 dsi@ae94000 { 383 compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 384 reg = <0x0ae94000 0x400>; 385 reg-names = "dsi_ctrl"; 386 387 #address-cells = <1>; 388 #size-cells = <0>; 389 390 interrupt-parent = <&mdss>; 391 interrupts = <4>; 392 393 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 394 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 395 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 396 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 397 <&dispcc DISP_CC_MDSS_AHB_CLK>, 398 <&dispcc DISP_CC_MDSS_AXI_CLK>; 399 clock-names = "byte", 400 "byte_intf", 401 "pixel", 402 "core", 403 "iface", 404 "bus"; 405 406 phys = <&dsi0_phy>; 407 phy-names = "dsi"; 408 409 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 410 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>; 411 412 power-domains = <&rpmhpd SC7180_CX>; 413 operating-points-v2 = <&dsi_opp_table>; 414 415 ports { 416 #address-cells = <1>; 417 #size-cells = <0>; 418 419 port@0 { 420 reg = <0>; 421 endpoint { 422 remote-endpoint = <&dpu_intf1_out>; 423 }; 424 }; 425 426 port@1 { 427 reg = <1>; 428 endpoint { 429 remote-endpoint = <&sn65dsi86_in>; 430 data-lanes = <0 1 2 3>; 431 qcom,te-source = "mdp_vsync_e"; 432 }; 433 }; 434 }; 435 }; 436... 437