xref: /linux/Documentation/devicetree/bindings/display/msm/dp-controller.yaml (revision 8a922b7728a93d837954315c98b84f6b78de0c4f) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MSM Display Port Controller
8
9maintainers:
10  - Kuogee Hsieh <quic_khsieh@quicinc.com>
11
12description: |
13  Device tree bindings for DisplayPort host controller for MSM targets
14  that are compatible with VESA DisplayPort interface specification.
15
16properties:
17  compatible:
18    enum:
19      - qcom,sc7180-dp
20      - qcom,sc7280-dp
21      - qcom,sc7280-edp
22      - qcom,sc8180x-dp
23      - qcom,sc8180x-edp
24      - qcom,sc8280xp-dp
25      - qcom,sc8280xp-edp
26      - qcom,sdm845-dp
27      - qcom,sm8350-dp
28
29  reg:
30    minItems: 4
31    items:
32      - description: ahb register block
33      - description: aux register block
34      - description: link register block
35      - description: p0 register block
36      - description: p1 register block
37
38  interrupts:
39    maxItems: 1
40
41  clocks:
42    items:
43      - description: AHB clock to enable register access
44      - description: Display Port AUX clock
45      - description: Display Port Link clock
46      - description: Link interface clock between DP and PHY
47      - description: Display Port Pixel clock
48
49  clock-names:
50    items:
51      - const: core_iface
52      - const: core_aux
53      - const: ctrl_link
54      - const: ctrl_link_iface
55      - const: stream_pixel
56
57  assigned-clocks:
58    items:
59      - description: link clock source
60      - description: pixel clock source
61
62  assigned-clock-parents:
63    items:
64      - description: phy 0 parent
65      - description: phy 1 parent
66
67  phys:
68    maxItems: 1
69
70  phy-names:
71    items:
72      - const: dp
73
74  operating-points-v2: true
75
76  opp-table: true
77
78  power-domains:
79    maxItems: 1
80
81  aux-bus:
82    $ref: /schemas/display/dp-aux-bus.yaml#
83
84  data-lanes:
85    $ref: /schemas/types.yaml#/definitions/uint32-array
86    deprecated: true
87    minItems: 1
88    maxItems: 4
89    items:
90      maximum: 3
91
92  "#sound-dai-cells":
93    const: 0
94
95  vdda-0p9-supply:
96    deprecated: true
97  vdda-1p2-supply:
98    deprecated: true
99
100  ports:
101    $ref: /schemas/graph.yaml#/properties/ports
102    properties:
103      port@0:
104        $ref: /schemas/graph.yaml#/properties/port
105        description: Input endpoint of the controller
106
107      port@1:
108        $ref: /schemas/graph.yaml#/$defs/port-base
109        description: Output endpoint of the controller
110        properties:
111          endpoint:
112            $ref: /schemas/media/video-interfaces.yaml#
113            unevaluatedProperties: false
114            properties:
115              data-lanes:
116                minItems: 1
117                maxItems: 4
118                items:
119                  enum: [ 0, 1, 2, 3 ]
120
121              link-frequencies:
122                minItems: 1
123                maxItems: 4
124                items:
125                  enum: [ 1620000000, 2700000000, 5400000000, 8100000000 ]
126
127    required:
128      - port@0
129      - port@1
130
131required:
132  - compatible
133  - reg
134  - interrupts
135  - clocks
136  - clock-names
137  - phys
138  - phy-names
139  - power-domains
140  - ports
141
142allOf:
143  # AUX BUS does not exist on DP controllers
144  # Audio output also is present only on DP output
145  # p1 regions is present on DP, but not on eDP
146  - if:
147      properties:
148        compatible:
149          contains:
150            enum:
151              - qcom,sc7280-edp
152              - qcom,sc8180x-edp
153              - qcom,sc8280xp-edp
154    then:
155      properties:
156        "#sound-dai-cells": false
157    else:
158      properties:
159        aux-bus: false
160        reg:
161          minItems: 5
162      required:
163        - "#sound-dai-cells"
164
165additionalProperties: false
166
167examples:
168  - |
169    #include <dt-bindings/interrupt-controller/arm-gic.h>
170    #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
171    #include <dt-bindings/power/qcom-rpmpd.h>
172
173    displayport-controller@ae90000 {
174        compatible = "qcom,sc7180-dp";
175        reg = <0xae90000 0x200>,
176              <0xae90200 0x200>,
177              <0xae90400 0xc00>,
178              <0xae91000 0x400>,
179              <0xae91400 0x400>;
180        interrupt-parent = <&mdss>;
181        interrupts = <12>;
182        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
183                 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
184                 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
185                 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
186                 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
187        clock-names = "core_iface", "core_aux",
188                      "ctrl_link",
189                      "ctrl_link_iface", "stream_pixel";
190
191        assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
192                          <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
193
194        assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
195
196        phys = <&dp_phy>;
197        phy-names = "dp";
198
199        #sound-dai-cells = <0>;
200
201        power-domains = <&rpmhpd SC7180_CX>;
202
203        ports {
204            #address-cells = <1>;
205            #size-cells = <0>;
206
207            port@0 {
208                reg = <0>;
209                endpoint {
210                    remote-endpoint = <&dpu_intf0_out>;
211                };
212            };
213
214            port@1 {
215                reg = <1>;
216                endpoint {
217                    remote-endpoint = <&typec>;
218                    data-lanes = <0 1>;
219                    link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
220                };
221            };
222        };
223    };
224...
225