xref: /linux/Documentation/devicetree/bindings/display/msm/dp-controller.yaml (revision 7f4f3b14e8079ecde096bd734af10e30d40c27b7) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MSM Display Port Controller
8
9maintainers:
10  - Kuogee Hsieh <quic_khsieh@quicinc.com>
11
12description: |
13  Device tree bindings for DisplayPort host controller for MSM targets
14  that are compatible with VESA DisplayPort interface specification.
15
16properties:
17  compatible:
18    oneOf:
19      - enum:
20          - qcom,sa8775p-dp
21          - qcom,sc7180-dp
22          - qcom,sc7280-dp
23          - qcom,sc7280-edp
24          - qcom,sc8180x-dp
25          - qcom,sc8180x-edp
26          - qcom,sc8280xp-dp
27          - qcom,sc8280xp-edp
28          - qcom,sdm845-dp
29          - qcom,sm8350-dp
30          - qcom,sm8650-dp
31      - items:
32          - enum:
33              - qcom,sm6350-dp
34              - qcom,sm8150-dp
35              - qcom,sm8250-dp
36              - qcom,sm8450-dp
37              - qcom,sm8550-dp
38          - const: qcom,sm8350-dp
39
40  reg:
41    minItems: 4
42    items:
43      - description: ahb register block
44      - description: aux register block
45      - description: link register block
46      - description: p0 register block
47      - description: p1 register block
48
49  interrupts:
50    maxItems: 1
51
52  clocks:
53    items:
54      - description: AHB clock to enable register access
55      - description: Display Port AUX clock
56      - description: Display Port Link clock
57      - description: Link interface clock between DP and PHY
58      - description: Display Port Pixel clock
59
60  clock-names:
61    items:
62      - const: core_iface
63      - const: core_aux
64      - const: ctrl_link
65      - const: ctrl_link_iface
66      - const: stream_pixel
67
68  assigned-clocks:
69    items:
70      - description: link clock source
71      - description: pixel clock source
72
73  assigned-clock-parents:
74    items:
75      - description: phy 0 parent
76      - description: phy 1 parent
77
78  phys:
79    maxItems: 1
80
81  phy-names:
82    items:
83      - const: dp
84
85  operating-points-v2: true
86
87  opp-table:
88    type: object
89
90  power-domains:
91    maxItems: 1
92
93  aux-bus:
94    $ref: /schemas/display/dp-aux-bus.yaml#
95
96  data-lanes:
97    $ref: /schemas/types.yaml#/definitions/uint32-array
98    deprecated: true
99    minItems: 1
100    maxItems: 4
101    items:
102      maximum: 3
103
104  "#sound-dai-cells":
105    const: 0
106
107  vdda-0p9-supply:
108    deprecated: true
109  vdda-1p2-supply:
110    deprecated: true
111
112  ports:
113    $ref: /schemas/graph.yaml#/properties/ports
114    properties:
115      port@0:
116        $ref: /schemas/graph.yaml#/properties/port
117        description: Input endpoint of the controller
118
119      port@1:
120        $ref: /schemas/graph.yaml#/$defs/port-base
121        unevaluatedProperties: false
122        description: Output endpoint of the controller
123        properties:
124          endpoint:
125            $ref: /schemas/media/video-interfaces.yaml#
126            unevaluatedProperties: false
127            properties:
128              data-lanes:
129                minItems: 1
130                maxItems: 4
131                items:
132                  enum: [ 0, 1, 2, 3 ]
133
134              link-frequencies:
135                minItems: 1
136                maxItems: 4
137                items:
138                  enum: [ 1620000000, 2700000000, 5400000000, 8100000000 ]
139
140    required:
141      - port@0
142      - port@1
143
144required:
145  - compatible
146  - reg
147  - interrupts
148  - clocks
149  - clock-names
150  - phys
151  - phy-names
152  - power-domains
153  - ports
154
155allOf:
156  # AUX BUS does not exist on DP controllers
157  # Audio output also is present only on DP output
158  # p1 regions is present on DP, but not on eDP
159  - if:
160      properties:
161        compatible:
162          contains:
163            enum:
164              - qcom,sc7280-edp
165              - qcom,sc8180x-edp
166              - qcom,sc8280xp-edp
167    then:
168      properties:
169        "#sound-dai-cells": false
170    else:
171      properties:
172        aux-bus: false
173        reg:
174          minItems: 5
175      required:
176        - "#sound-dai-cells"
177
178additionalProperties: false
179
180examples:
181  - |
182    #include <dt-bindings/interrupt-controller/arm-gic.h>
183    #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
184    #include <dt-bindings/power/qcom-rpmpd.h>
185
186    displayport-controller@ae90000 {
187        compatible = "qcom,sc7180-dp";
188        reg = <0xae90000 0x200>,
189              <0xae90200 0x200>,
190              <0xae90400 0xc00>,
191              <0xae91000 0x400>,
192              <0xae91400 0x400>;
193        interrupt-parent = <&mdss>;
194        interrupts = <12>;
195        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
196                 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
197                 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
198                 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
199                 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
200        clock-names = "core_iface", "core_aux",
201                      "ctrl_link",
202                      "ctrl_link_iface", "stream_pixel";
203
204        assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
205                          <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
206
207        assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
208
209        phys = <&dp_phy>;
210        phy-names = "dp";
211
212        #sound-dai-cells = <0>;
213
214        power-domains = <&rpmhpd SC7180_CX>;
215
216        ports {
217            #address-cells = <1>;
218            #size-cells = <0>;
219
220            port@0 {
221                reg = <0>;
222                endpoint {
223                    remote-endpoint = <&dpu_intf0_out>;
224                };
225            };
226
227            port@1 {
228                reg = <1>;
229                endpoint {
230                    remote-endpoint = <&typec>;
231                    data-lanes = <0 1>;
232                    link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
233                };
234            };
235        };
236    };
237...
238